LAN9420 Datasheet, PDF (30/171 Pages) SMSC Corporation – Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface

3.3.2
3.3.3
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface
Datasheet
write of '1' to the corresponding status bit in the INT_STS register. The remaining interrupts are cleared
from the source CSR.
The Interrupt Controller receives the wake event detection interrupt (WAKE_INT) from the wake
detection logic. If enabled, the wake detection logic is able to generate an interrupt to the PCI Bridge
on detection of a MAC wakeup event (Wakeup Frame or Magic Packet), or on an Ethernet link status
change (energy detect).
Note: LAN9420/LAN9420i can optionally generate a PCI interrupt in addition to assertion of nPME
on detection of a power management event. Generation of a PCI interrupt is not the typical
usage.
Unlike the other interrupt sources, the software interrupt (SW_INT) is asserted on a 0-to-1 transition
of its enable bit (SW_INT_EN). The DMAC interrupt is enabled in the DMA controller. All other
Interrupts are enabled through the INT_EN register. Setting an enable bit high enables the
corresponding interrupt as a source of the IRQ.
The Interrupt Controller contains an interrupt de-assertion timer. This timer guarantees a minimum
interrupt de-assertion period for the IRQ. The de-assertion timer has a resolution of 10us and is
programmable through the INT_CFG SCSR (refer to Section 4.2.4, "Interrupt Configuration Register
(INT_CFG)," on page 92). A setting of all zeros disables the de-assertion timer. The state of the
interrupt de-assertion timer is reflected by the interrupt de-assertion timer status bit (INT_DEAS_STS)
bit in the IRQ_CFG register. When this bit is set, the de-assertion timer is currently in a de-assertion
interval, and, with the exception of the WAKE_INT, all pending interrupts are blocked.
Note: The interrupt de-assertion timer does not affect WAKE_INT. This interrupt event is able to
assert IRQ regardless of the state of the de-assertion timer.
The IRQ_INT status bit in the INT_CFG register reflects the aggregate status of all interrupt sources.
If this status bit is set, one or more enabled interrupts are active. The IRQ_INT status bit is not affected
by the de-assertion timer.
The IRQ output is enabled/disabled by the IRQ_EN enable bit in the INT_CTL register. When this bit
is cleared, with the exception of WAKE_INT, all interrupts to the PCI Bridge are disabled. When set,
interrupts to the PCI Bridge are enabled.
Note: The IRQ_EN does not affect WAKE_INT. This interrupt event is able to assert IRQ regardless
of the state of IRQ_EN.
Wake Event Detection Logic
LAN9420/LAN9420i supports the ability to generate wake interrupts on detection of a Magic Packet,
Wakeup Frame or Ethernet link status change (energy detect). When enabled to do so, the wake event
detection logic generates an interrupt to the Interrupt Controller. Refer to Section 3.7.6, "Detecting
Power Management Events," on page 81 for more information on the wake event interrupt.
Wakeup frame detection must be enabled in the MAC before detection can occur. Likewise, the energy
detect interrupt must be enabled in the PHY before this interrupt can be used.
General Purpose Timer (GPT)
The General Purpose Timer is a programmable device that can be used to generate periodic system
interrupts. The resolution of this timer is 100uS.
The GP Timer loads the GPT_CNT Register with the value in the GPT_LOAD field and begins counting
when the TIMER_EN bit is asserted (1). On a chip-level reset, or when the TIMER_EN bit changes
from asserted (1) to de-asserted (0), the GPT_LOAD field is initialized to FFFFh. The GPT_CNT
register is also initialized to FFFFh on a reset. Software can write the pre-load value into the
GPT_LOAD field at any time (e.g., before or after the TIMER_EN bit is asserted). The GPT Enable bit
TIMER_EN is located in the GPT_CFG register.
Revision 1.6 (07-18-11)
30
DATASHEET
SMSC LAN9420/LAN9420i