LAN9420 Datasheet, PDF (110/171 Pages) SMSC Corporation – Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface

4.3.6
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface
Datasheet
DMA Controller Status Register (DMAC_STATUS)
Offset:
0014h
Size:
32 bits
This register contains all of the status bits that the DMAC reports to the Host system. Most of the fields
in this register will cause an interrupt. Status can be checked as part of an interrupt service routine, or
by polling. DMAC interrupts can be masked in the DMAC_INTR_ENA register.
BITS
31:23
22:20
DESCRIPTION
RESERVED
Transmit Process State (TS)
This Read-Only field indicates the state of the transmit process. This field
does not generate an interrupt. The TS field is encoded as follows:
STATE
000
001
010
011
100
101
110
111
DESCRIPTION
Stopped - Reset or Stop command issued
Running - Fetching the transmit descriptor
Running - Waiting for the end of transmission
Running - Reading the data from memory and queuing into TX FIFO
RESERVED
RESERVED
Suspended - Unavailable transmit descriptor
Running - Closing the transmit descriptor
TYPE
RO
RO
DEFAULT
-
000b
19:17
Receive Process State (RS)
This Read-Only field indicates the state of the receive process. This field
does not generate an interrupt. The RS field is encoded as follows:
STATE
000
001
010
011
100
101
110
111
DESCRIPTION
Stopped - Reset or Stop receive command
Running - Fetching the receive descriptor
Running - Checking for end of receive packet before prefetch of next
descriptor
Running - Waiting for receive packet
Suspended - Unavailable receive descriptor
Running - Closing receive descriptor
Running - Flushing the current frame from the receive buffer because
of unavailable receive buffer
Running - Queuing the receive frame from the receive buffer into the
Host memory
16 Normal Interrupt Summary (NIS)
This bit is the logical OR of other bits within this register. Only unmasked
bits affect this register. Below is the list of bits:
DMAC_STATUS[0]: Transmit interrupt (TI)
DMAC_STATUS[2]: Transmit buffer unavailable (TU)
DMAC_STATUS[6]: Receive interrupt (RI)
RO
R/WC
000b
0b
Revision 1.6 (07-18-11)
110
DATASHEET
SMSC LAN9420/LAN9420i