LAN9420 Datasheet, PDF (104/171 Pages) SMSC Corporation – Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface

Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface
Datasheet
4.3 DMAC Control and Status Registers (DCSR)
Table 4.4 lists the registers contained in this section.
Table 4.4 DMAC Control and Status Register (DCSR) Map
OFFSET
0000h
0004h
0008h
000Ch
0010h
0014h
0018h
001Ch
0020h
0024h – 004Ch
0050h
0054h
0058h – 007Ch
SYMBOL
REGISTER NAME
BUS_MODE
Bus Mode Register
TX_POLL_DEMAND Transmit Poll Demand Register
RX_POLL_DEMAND Receive Poll Demand Register
RX_ BASE_ADDR
Receive List Base Address Register
TX_BASE_ADDR
Transmit List Base Address Register
DMAC_STATUS
DMA Controller Status Register
DMAC_CONTROL
DMA Controller Control (Operation Mode) Register
DMAC_INTR_ENA
DMA Controller Interrupt Enable Register
MISS_FRAME_CNTR Missed Frame Counter (RX Only)
RESERVED
Reserved for future expansion
CUR_TX_BUF_ADDR Current Transmit Buffer Address
CUR_RX_BUF_ADDR Current Receive Buffer Address
RESERVED
Reserved for future expansion
Revision 1.6 (07-18-11)
104
DATASHEET
SMSC LAN9420/LAN9420i