LAN9420 Datasheet, PDF (60/171 Pages) SMSC Corporation – Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface

3.5.4.1
3.5.5
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface
Datasheet
Magic Packet Detection
Setting the Magic Packet Enable bit (MPEN) in the Section 4.4.12, "Wakeup Control and Status
Register (WUCSR)," on page 134, places the MAC in the “Magic Packet” detection mode. In this mode,
normal data reception is disabled, and detection logic within the MAC examines receive data for a
Magic Packet. The MAC can be programmed to assert the wake event interrupt to the Interrupt
Controller on detection. Upon detection, the Magic Packet Received bit (MPR) in the WUCSR is set.
When the Host clears the MPEN bit, normal receive operation will resume. Please refer to Section
4.4.12, "Wakeup Control and Status Register (WUCSR)," on page 134 for additional information on this
register
In Magic Packet mode, logic within the MAC constantly monitors each frame addressed to the node
for a specific Magic Packet pattern. It checks only packets with the MAC’s address or a broadcast
address to meet the Magic Packet requirement. The MAC checks each received frame for the pattern
48’hFF_FF_FF_FF_FF_FF after the destination and source address field.
Then the MAC inspects the frame for 16 repetitions of the MAC address without any breaks or
interruptions. In case of a break in the 16 address repetitions, the MAC scans for the
48'hFF_FF_FF_FF_FF_FF pattern again in the incoming frame.
The 16 repetitions may be anywhere in the frame but must be preceded by the synchronization stream.
The device will also accept a multicast frame, as long as it detects the 16 duplications of the MAC
address. If the MAC address of a node is 00h 11h 22h 33h 44h 55h, then the MAC scans for the
following data sequence in an Ethernet frame:
Destination Address Source Address ……………FF FF FF FF FF FF
00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55
00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55
00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55
00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55
…CRC
It should be noted that Magic Packet detection can be performed when LAN9420/LAN9420i is in any
power management state.
Receive Checksum Offload Engine (RXCOE)
The receive checksum offload engine (RXCOE) provides assistance to the Host by calculating a 16-
bit checksum for a received Ethernet frame. The RXCOE readily supports the following IEEE802.3
frame formats:
„ Type II Ethernet frames
„ SNAP encapsulated frames
„ Support for up to 2, 802.1q VLAN tags
The resulting checksum value can also be modified by software to support other frame formats.
The RXCOE has two modes of operation. In mode 0, the RXCOE calculates the checksum between
the first 14 bytes of the Ethernet frame and the FCS. This is illustrated in Figure 3.19.
Revision 1.6 (07-18-11)
60
DATASHEET
SMSC LAN9420/LAN9420i