LAN9420 Datasheet, PDF (105/171 Pages) SMSC Corporation – Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface

Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface
Datasheet
4.3.1 Bus Mode Register (BUS_MODE)
Offset:
0000h
Size:
32 bits
This register establishes the bus operating modes for the DMAC.
BITS
31:21
20
19:14
13:8
7
6:2
1
0
DESCRIPTION
RESERVED
Descriptor Byte Ordering (DBO)
When set, the device operates in big-endian mode for descriptors. In big-
endian mode descriptor byte lanes 0-3 and 1-2 are swapped. CSR bit
positions within each byte are not changed.
This bit should be cleared to ‘0’ for normal operation.
RESERVED
Programmable Burst Length (PBL)
Indicates the maximum number of DWORDs to be transferred in one DMA
transaction. This will be the maximum value that is used in a single block
read/write. The DMAC will always attempt to burst transfer the length
specified in the PBL each time it starts a burst transfer.
PBL can be programmed with permissible values of 1, 2, 4, 8, 16 and 32.
Any other value will result in undefined behavior.
Note: PCI bursts are always 16 cycles, regardless of the value in this
field.
Big-Endian/Little-Endian (BLE)
Specifies the byte ordering for data buffers. When set, the DMAC operates
in big-endian mode when accessing data buffers in Host memory. In big-
endian mode buffer byte lanes 0-3 and 1-2 are swapped.
This bit should be cleared to ‘0’ for normal operation.
Descriptor Skip Length (DSL)
Specifies the number of DWORDs to skip between two unchained
descriptors.
Bus Arbitration (BAR)
When this bit is set the RX DMA operations are given priority while
guarantying TX at least one grant in between consecutive RX packets.
When cleared, the arbitration ratio is dictated by the BUS_CFG[26:25] field.
Software Reset (SRST)
When this bit is set, the DMAC and MAC are reset. This is a self-clearing
bit.
Note: It will take up to 120ns for the SRST to complete
TYPE
RO
R/W
RO
R/W
R/W
R/W
R/W
R/W/SC
DEFAULT
-
0b
-
001000b
0b
00000b
0b
0b
SMSC LAN9420/LAN9420i
105
DATASHEET
Revision 1.6 (07-18-11)