LAN9420 Datasheet, PDF (130/171 Pages) SMSC Corporation – Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface

4.4.8
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface
Datasheet
Flow Control Register (FLOW)
Offset:
009Ch
Size:
32 bits
This register is used to control the generation and reception of the Control frames by the MAC’s flow
control block. A write to this register with busy bit set to 1 will trigger the Flow control block to generate
a Control frame. Before writing to this register, the application has to make sure that the busy bit is
not set.
BITS
31:16
15:3
2
1
0
DESCRIPTION
Pause Time (FCPT)
This field indicates the value to be used in the PAUSE TIME field in the
control frame.
RESERVED
Pass Control Frames (FCPASS)
When set, the MAC sets the packet filter bit in the receive packet status to
indicate to the application that a valid pause frame has been received. The
application must accept or discard a received frame based on the packet
filter control bit. The MAC receives, decodes and performs the pause
function when a valid pause frame is received in full-duplex mode and when
flow control is enabled (FCE bit set). When reset, the MAC resets the
packet filter bit in the receive packet status.
The MAC always passes the data of all frames it receives (including flow
control frames) to the application. Frames that do not pass address filtering,
as well as frames with errors, are passed to the application. The application
must discard or retain the received frame’s data based on the received
frame’s STATUS field. Filtering modes (promiscuous mode, for example)
take precedence over the FCPASS bit.
Flow Control Enable (FCEN)
When set, enables the MAC flow control function. The MAC decodes all
incoming frames for control frames; if it receives a valid control frame
(PAUSE command), it disables the transmitter for a specified time (decoded
pause time x slot time). When reset, the MAC flow control function is
disabled; the MAC does not decode frames for control frames.
Note: Flow Control is applicable when the MAC is set in full duplex
mode.
Flow Control Busy (FCBSY)
In full-duplex mode this bit should read logical 0 before writing to the flow
control register. To initiate a PAUSE control frame, the Host system must
set this bit to 1. During a transfer of control frame, this bit continues to be
set, signifying that a frame transmission is in progress. After the PAUSE
control frame’s transmission is complete, the MAC resets to 0.
TYPE
R/W
RO
R/W
R/W
R/W
DEFAULT
0000h
-
0b
0b
0b
Revision 1.6 (07-18-11)
130
DATASHEET
SMSC LAN9420/LAN9420i