LAN9420 Datasheet, PDF (32/171 Pages) SMSC Corporation – Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface

Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface
Datasheet
Table 3.2 EEPROM Format (continued)
EEPROM BYTE ADDRESS
9
0Ah
EEPROM CONTENTS
Subsystem Vendor ID [7:0]
Subsystem Vendor ID [15:8]
Note: EEPROM byte addresses past 0Ah can be used to store data for any purpose.
The signature value of 0xA5 is stored at address 0. A different signature value indicates to the
EEPROM controller that no EEPROM or an un-programmed EEPROM is attached to
LAN9420/LAN9420i. In this case, following default values are used for the Subsystem Device ID
(SSID), Subsystem Vendor ID (SSVID), and the MAC address.
Table 3.3 EEPROM Variable Defaults
VARIABLE
Subsystem ID [15:0]
Subsystem Vendor ID [15:0]
MAC Address [47:0]
DEFAULT
0x9420
0x1055
0xFFFF_FFFF_FFFF
3.3.5.2
3.3.5.3
MAC Address, Subsystem ID, and Subsystem Vendor ID Auto-Load
On a system-level reset, the EEPROM controller attempts to read the first byte of data from the
EEPROM (address 00h). If the value A5h is read from the first address, then the EEPROM controller
will assume that an external EEPROM is present. The EEPROM controller will then access the next
EEPROM byte and send it to the MAC Address register byte 0 (ADDRL[7:0]). This process will be
repeated for the next five bytes of the MAC Address, thus fully programming the 48-bit MAC address.
The Subsystem ID and Subsystem Vendor ID are similarly extracted from the EEPROM and are used
to set the value of the analogous PCI Header registers contained within the PCIB. Once all eleven
bytes have been programmed, the “EEPROM Loaded” bit is set in the E2P_CMD register. A detailed
explanation of the EEPROM byte ordering with respect to the MAC address is given in Section 4.4.3,
"MAC Address Low Register (ADDRL)," on page 125.
If an 0xA5h is not read from the first address, the EEPROM controller will end initialization. The default
values, as specified in Table 3.3, will then be assumed by the associated registers. It is then the
responsibility of the Host LAN driver software to set the IEEE address by writing to the MAC’s ADDRH
and ADDRL registers.
EEPROM Host Operations
After the EEPROM controller has finished reading (or attempting to read) the EEPROM after a system-
level reset, the Host is free to perform other EEPROM operations. EEPROM operations are performed
using the EEPROM Command (E2P_CMD) and EEPROM Data (E2P_DATA) registers. Section 4.2.11,
"EEPROM Command Register (E2P_CMD)," on page 100 provides an explanation of the supported
EEPROM operations.
If the EEPROM operation is the “write location” (WRITE) or “write all” (WRAL) commands, the Host
must first write the desired data into the E2P_DATA register. The Host must then issue the WRITE or
WRAL command using the E2P_CMD register by setting the EPC_CMD field appropriately. If the
operation is a WRITE, the EPC_ADDR field in E2P_CMD must also be set to the desired location. The
command is executed when the Host sets the EPC_BSY bit high. The completion of the operation is
indicated when the EPC_BSY bit is cleared.
Revision 1.6 (07-18-11)
32
DATASHEET
SMSC LAN9420/LAN9420i