LAN9420 Datasheet, PDF (69/171 Pages) SMSC Corporation – Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface

Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface
Datasheet
3.6.2.4
3.6.2.5
3.6.2.6
3.6.2.7
3.6.3
Descrambling
The descrambler performs an inverse function to the scrambler in the transmitter and also performs
the Serial In Parallel Out (SIPO) conversion of the data.
During reception of IDLE (/I/) symbols. the descrambler synchronizes its descrambler key to the
incoming stream. Once synchronization is achieved, the descrambler locks on this key and is able to
descramble incoming data.
Special logic in the descrambler ensures synchronization with the remote PHY by searching for IDLE
symbols within a window of 4000 bytes (40us). This window ensures that a maximum packet size of
1514 bytes, allowed by the IEEE 802.3 standard, can be received with no interference. If no IDLE-
symbols are detected within this time-period, receive operation is aborted and the descrambler re-starts
the synchronization process.
The descrambler can be bypassed by setting bit 0 of register 31.
Alignment
The de-scrambled signal is then aligned into 5-bit code-groups by recognizing the /J/K/ Start-of-Stream
Delimiter (SSD) pair at the start of a packet. Once the code-word alignment is determined, it is stored
and utilized until the next start of frame.
5B/4B Decoding
The 5-bit code-groups are translated into 4-bit data nibbles according to the 4B/5B table. The SSD,
/J/K/, is translated to “0101 0101” as the first 2 nibbles of the MAC preamble. Reception of the SSD
causes the PHY to assert the internal RX_DV signal, indicating that valid data is available on the
Internal RXD bus. Successive valid code-groups are translated to data nibbles. Reception of either the
End of Stream Delimiter (ESD) consisting of the /T/R/ symbols, or at least two /I/ symbols causes the
PHY to de-assert the internal carrier sense and RX_DV.
These symbols are not translated into data.
Receiver Errors
During a frame, unexpected code-groups are considered receive errors. Expected code groups are the
DATA set (0 through F), and the /T/R/ (ESD) symbol pair. When a receive error occurs, the internal
MII’s RX_ER signal is asserted and arbitrary data is driven onto the internal receive data bus (RXD)
to the MAC. Should an error be detected during the time that the /J/K/ delimiter is being decoded (bad
SSD error), RX_ER is asserted and the value 1110b is driven onto the internal receive data bus (RXD)
to the MAC. Note that the internal MII’s data valid signal (RX_DV) is not yet asserted when the bad
SSD occurs.
10BASE-T Transmit
Data to be transmitted comes from the MAC. The 10BASE-T transmitter receives 4-bit nibbles from
the internal MII at a rate of 2.5MHz and converts them to a 10Mbps serial data stream. The data
stream is then Manchester-encoded and sent to the analog transmitter, which drives a signal onto the
twisted pair via the external magnetics.
The 10M transmitter uses the following blocks:
„ MII (digital)
„ TX 10M (digital)
„ 10M Transmitter (analog)
„ 10M PLL (analog)
SMSC LAN9420/LAN9420i
69
DATASHEET
Revision 1.6 (07-18-11)