LAN9420 Datasheet, PDF (71/171 Pages) SMSC Corporation – Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface

Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface
Datasheet
3.6.5
the line, within 45ms. Once TX_EN is de-asserted, the logic resets the jabber condition. Bit 1 of the
Basic Status register indicates that a jabber condition was detected.
Auto-negotiation
The purpose of the Auto-negotiation function is to automatically configure the PHY to the optimum link
parameters based on the capabilities of its link partner. Auto-negotiation is a mechanism for
exchanging configuration information between two link-partners and automatically selecting the highest
performance mode of operation supported by both sides. Auto-negotiation is fully defined in clause 28
of the IEEE 802.3 specification.
Once auto-negotiation has completed, information about the resolved link can be passed back to the
controller via the internal Serial Management Interface (SMI). The results of the negotiation process
are reflected in the Speed Indication bits in register 31, as well as the Auto Negotiation Link Partner
Ability Register (Register 5).
The auto-negotiation protocol is a purely physical layer activity and proceeds independently of the MAC
controller.
The advertised capabilities of the PHY are stored in register 4 of the SMI registers. The default
advertised by the PHY is determined by user-defined on-chip signal options.
The following blocks are activated during an Auto-negotiation session:
„ Auto-negotiation (digital)
„ 100M ADC (analog)
„ 100M PLL (analog)
„ 100M equalizer/BLW/clock recovery (DSP)
„ 10M SQUELCH (analog)
„ 10M PLL (analog)
„ 10M Transmitter (analog)
When enabled, auto-negotiation is started by the occurrence of one of the following events:
„ Chip-level reset
„ Software reset
„ Link status down
„ Setting register 0, bit 9 high (auto-negotiation restart)
On detection of one of these events, the PHY begins auto-negotiation by transmitting bursts of Fast
Link Pulses (FLP). These are bursts of link pulses from the 10M transmitter. They are shaped as
Normal Link Pulses and can pass uncorrupted down CAT-3 or CAT-5 cable. A Fast Link Pulse Burst
consists of up to 33 pulses. The 17 odd-numbered pulses, which are always present, frame the FLP
burst. The 16 even-numbered pulses, which may be present or absent, contain the data word being
transmitted. Presence of a data pulse represents a “1”, while absence represents a “0”.
The data transmitted by an FLP burst is known as a “Link Code Word.” These are defined fully in IEEE
802.3 clause 28. In summary, the PHY advertises 802.3 compliance in its selector field (the first 5 bits
of the Link Code Word). It advertises its technology ability according to the bits set in register 4 of the
SMI registers.
There are 4 possible matches of the technology abilities. In the order of priority these are:
„ 100M full-duplex (Highest priority)
„ 100M half-duplex
„ 10M full-duplex
„ 10M half-duplex
SMSC LAN9420/LAN9420i
71
DATASHEET
Revision 1.6 (07-18-11)