LAN9420 Datasheet, PDF (53/171 Pages) SMSC Corporation – Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface

Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface
Datasheet
3.4.11
the corresponding summary bit is cleared. When both the summary bits are cleared, the DMAC
interrupt is de-asserted.
Interrupts are not queued and if a second interrupt event occurs before the driver has responded to
the first interrupt, no additional interrupts will be generated. For example, Receive Interrupt (RI bit in
the DMAC_STATUS register) indicates that one or more frames was transferred to a Host memory
buffer. The driver must scan all descriptors, from the last recorded position to the first one owned by
the DMA controller.
An interrupt is generated only once for simultaneous, multiple events. The driver must scan the
DMAC_STATUS register for the interrupt cause. The interrupt is not generated again, unless a new
interrupting event occurs after the driver has cleared the appropriate DMAC_STATUS bit. For example,
the controller generates a receive interrupt (RI) and the driver begins reading DMAC_STATUS. Next,
a Receive Buffer Unavailable (RU) occurs. The driver clears the receive interrupt. DMA_INTR gets de-
asserted for at least one cycle and then asserted again for the RX buffer unavailable interrupt.
DMAC Control and Status Registers (DCSR)
Please refer Section 4.3, "DMAC Control and Status Registers (DCSR)," on page 104 to for a complete
description of the DCSR.
3.5
10/100 Ethernet MAC
The Ethernet Media Access Controller (MAC) provides the following features:
„ Compliant with the IEEE 802.3 and 802.3u specifications
„ Supports 10-Mbps and 100-Mbps data transfer rates
„ Transmit and receive message data encapsulation
„ Framing (frame boundary delimitation, frame synchronization)
„ Error detection (physical medium transmission errors)
„ Media access management
„ Medium allocation (collision detection, except in full-duplex operation)
„ Contention resolution (collision handling, except in full-duplex operation)
„ Decoding of control frames (PAUSE command) and disabling the transmitter
„ Generation of control frames
„ Internal MII interface for communication with the embedded PHY
„ Supports Virtual Local Area Network (VLAN) operations
„ Supports both full- and half-duplex operations
„ Support of CSMA/CD Protocol for half-duplex Mode
„ Supports flow control for full-duplex operation
„ Wake detection logic, which detects Wakeup Frames and Magic Packets
„ Collision detection and auto retransmission on collisions in Half-Duplex Mode
„ Preamble generation and removal
„ Automatic 32-bit CRC generation and checking
„ Options to insert PAD/CRC32 on transmit
„ Options to set Automatic Pad stripping in Receive packets
„ Checksum offload engine for calculation of layer 3 transmit and receive checksum
SMSC LAN9420/LAN9420i
53
DATASHEET
Revision 1.6 (07-18-11)