LAN9420 Datasheet, PDF (57/171 Pages) SMSC Corporation – Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface

Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface
Datasheet
3.5.3.3
3.5.3.4
3.5.4
multicast hash table low register and a value of 11111 selects Bit 31 of the multicast hash table high
register.
Hash Perfect Filtering
In hash perfect filtering, if the received frame is a physical address, the packet filter block perfect-filters
the incoming frame’s destination field with the value programmed into the MAC Address High register
(refer to Section 4.4.2, "MAC Address High Register (ADDRH)," on page 124) and the MAC address
low register (refer to Section 4.4.3, "MAC Address Low Register (ADDRL)," on page 125). If the
incoming frame is a multicast frame, however, the packet filter function performs an imperfect address
filtering against the hash table.
The imperfect filtering against the hash table is the same imperfect filtering process described in
Section 3.5.3.2.
Inverse Filtering
During inverse filtering, the packet filter block accepts incoming frames with a destination address not
matching the perfect address (i.e., the value programmed into the MAC Address High register and the
MAC Address Low register in the CRC block) and rejects frames with destination addresses matching
the perfect address.
For all filtering modes, when MCPAS is set, all multicast frames are accepted. When the PRMS bit is
set, all frames are accepted regardless of their destination address. This includes all broadcast frames
as well.
Wakeup Frame Detection
Setting the Wakeup Frame Enable bit (WAKE_EN) in the “WUCSR—Wakeup Control and Status
Register”, places the MAC in the wakeup frame detection mode. In this mode, normal data reception
is disabled, and detection logic within the MAC examines receive data for the pre-programmed wakeup
frame patterns. Upon detection of a wake event, the MAC will assert the wake event interrupt to the
Interrupt Controller. In turn, the Interrupt Controller can be programmed to assert its interrupt (IRQ) to
the PCIB. In reduced power modes, the IRQ interrupt can be used to generate a wakeup event using
the nPME signal, which, if enabled to do so, will return the system to its normal operational state (S0
state). The IRQ interrupt can also be used to generate an interrupt to the Host, via the nINT signal.
Upon detection, the Wakeup Frame Received bit (WUFR) in the WUCSR is set. When the Host system
clears the WUEN bit, the MAC will resume normal receive operation.
Before putting the MAC into the wakeup frame detection state, the Host application must provide the
detection logic with a list of sample frames and their corresponding byte masks. This information is
written into the Wakeup Frame Filter register (WUFF). Please refer to Section 4.4.11, "Wakeup Frame
Filter (WUFF)," on page 133 for additional information on this register.
The MAC supports four programmable filters that support many different receive packet patterns. If
remote wakeup mode is enabled, the remote wakeup function receives all frames addressed to the
MAC. It then checks each frame against the enabled filter and recognizes the frame as a remote
wakeup frame if it passes the wakeup frame filter register’s address filtering and CRC value match.
In order to determine which bytes of the frames should be checked by the CRC module, the MAC uses
a programmable byte mask and a programmable pattern offset for each of the four supported filters.
The pattern’s offset defines the location of the first byte that should be checked in the frame. The byte
mask is a 31-bit field that specifies whether or not each of the 31 contiguous bytes within the frame,
beginning in the pattern offset, should be checked. If bit j in the byte mask is set, the detection logic
checks byte offset + j in the frame.
In order to load the Wakeup Frame Filter register, the LAN driver software must perform eight writes
to the Wakeup Frame Filter register (WUFF). Table 3.14 shows the Wakeup Frame Filter register’s
structure.
SMSC LAN9420/LAN9420i
57
DATASHEET
Revision 1.6 (07-18-11)