LAN9420 Datasheet, PDF(37/171 Page) SMSC Corporation – Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface

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LAN9420 Datasheet, PDF (37/171 Pages) SMSC Corporation – Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface

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Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface

Datasheet

WRAL (Write All): If erase/write operations are enabled in the EEPROM, this command will cause the

contents of the E2P_DATA register to be written to every EEPROM memory location. The EPC_TO bit

is set if the EEPROM does not respond within 30ms.

EECS

EECLK

EEDIO (OUTPUT)

EEDIO (INPUT)

tCSL

Figure 3.14 EEPROM WRAL Cycle

Table 3.4, "Required EECLK Cycles", shown below, shows the number of EECLK cycles required for

each EEPROM operation.

OPERATION

ERASE

ERAL

EWDS

EWEN

READ

WRITE

WRAL

Table 3.4 Required EECLK Cycles

REQUIRED EECLK CYCLES

3.3.5.3.2

3.3.5.3.3

3.3.5.3.4

HOST INITIATED MAC ADDRESS, SSID, SSVID RELOAD

The Host can initiate a reload of the MAC address, SSID, and SSVID from the EEPROM by issuing

the RELOAD command via the E2P command (E2P_CMD) register. If the first byte read from the

EEPROM is not A5h, it is assumed that the EEPROM is not present, or not programmed, and the

RELOAD operation will fail. The âEEPROM Loadedâ bit indicates a successful reload of the MAC

address, SSID, and SSVID.

EEPROM COMMAND AND DATA REGISTERS

Refer to Section 4.2.11, "EEPROM Command Register (E2P_CMD)," on page 100 and Section 4.2.12,

"EEPROM Data Register (E2P_DATA)," on page 103 for a detailed description of these registers.

Supported EEPROM operations are described in these sections.

EEPROM TIMING

Refer to Section 5.8, "EEPROM Timing," on page 166 for detailed EEPROM timing specifications.

SMSC LAN9420/LAN9420i

DATASHEET

Revision 1.6 (07-18-11)

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