LAN9420 Datasheet, PDF (90/171 Pages) SMSC Corporation – Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface

4.2.3
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface
Datasheet
Interrupt Status Register (INT_STS)
Offset:
00C8h
Size:
32 bits
This register contains the current status of the generated interrupts. Some of these interrupts are also
cleared through this register.
BITS
31:16
15
14
13
12
11:7
6:4
3
2
DESCRIPTION
RESERVED
Software Interrupt (SW_INT)
This bit latches high upon the SW_INT_EN bit toggling from a 0 to 1. The
interrupt is cleared by writing a ‘1’. Writing ‘0’ has no effect.
RESERVED
Master Bus Error Interrupt (MBERR_INT)
When set, indicates DMA Controller has detected an error during descriptor
read, or during a transmit data read operation. The interrupt is cleared by
writing a ‘1’ to this bit. Writing a ‘0’ has no effect.
To guarantee a clean recovery from a MBERR_INT condition, a software
reset must be performed by setting the Software Reset (SRST) bit of the
Bus Mode Register (BUS_MODE). Alternatively, the condition may be
cleared by a hardware reset.
Slave Bus Error Interrupt (SBERR_INT)
When set, indicates that the PCI Target Interface has detected an error
when the Host attempted to access the LAN9420/LAN9420i CSR. The
interrupt is cleared by writing a ‘1’ to this bit. Writing a ‘0’ has no effect.
To guarantee a clean recovery from a SBERR_INT condition, a software
reset must be performed by setting the Software Reset (SRST) bit of the
Bus Mode Register (BUS_MODE). Alternatively, the condition may be
cleared by a hardware reset
RESERVED
GPIO [2:0] (GPIOx_INT)
Interrupts are generated from the GPIO’s. These interrupts are configured
through the GPIO_CFG register. Refer to 4.2.5, "General Purpose
Input/Output Configuration Register (GPIO_CFG)," on page 93 for more
information. These interrupts are cleared by writing a ‘1’ to the
corresponding bits. Writing ‘0’ has no effect.
GP Timer (GPT_INT)
This interrupt is issued when the General Purpose Timer wraps from
maximum count to zero. This interrupt is cleared by writing a ‘1’ to this bit.
Writing ‘0’ has no effect.
PHY Interrupt (PHY_INT)
Indicates assertion of the PHY Interrupt. The PHY interrupt is cleared by
clearing the interrupt source in the PHY Interrupt Status Register. Refer to
Section 4.5.11, "Interrupt Source Flag," on page 147 for more information
on this interrupt. Writing to this bit has no effect.
TYPE
RO
R/WC
RO
R/WC
R/WC
RO
R/WC
R/WC
RO
DEFAULT
-
0b
-
0b
0b
-
000b
0b
0b
Revision 1.6 (07-18-11)
90
DATASHEET
SMSC LAN9420/LAN9420i