LAN9420 Datasheet, PDF (82/171 Pages) SMSC Corporation – Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface

3.7.6.1
3.7.7
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface
Datasheet
(WAKE_INT) status bit in the Interrupt Status Register (INT_STS). If so enabled, setting this status bit
will cause the assertion of nINT.
Enabling Wakeup Frame Wake Events
The Host system must perform the following steps to enable LAN9420/LAN9420i to assert a PCI wake
event (nPME) on detection of a Wakeup frame.
1. All transmit and receive operations must be halted:
a. All pending Ethernet TX and RX operations must be completed, and then the DMA controller and
MAC must be halted.
b. The software application must wait for all pending DMA transactions to complete. Upon completion,
no further transactions are permitted.
2. The MAC must be configured to detect the desired wake event. This process is explained in
Section 3.5.4, "Wakeup Frame Detection," on page 57.
3. Bit 1 of the Wakeup Status (WUPS[1]) in the Power Management Control Register (PMT_CTRL)
must be cleared since a set bit will cause the immediate assertion of wake event when WOL_EN
is set. The WUPS[1] bit will not clear if the internal MAC wakeup event is asserted.
4. Set the Wake-On-Lan Wakeup Enable (WOL_EN) bit in the Power Management Control Register
(PMT_CTRL).
5. Set the PME Enable (PME_EN) bit in the PCI Power Management Control and Status Register
(PCI_PMCSR). Note that PME_EN must be set before entering the D3 state. If this bit is not set,
the internal PHY will be reset and placed in the General Power-Down state and the device will not
be able to detect wakeup frames.
6. To place the device in the D3 state, set the Power Management State (PM_STATE) field of the PCI
Power Management Control and Status Register (PCI_PMCSR) to 11b (‘D3’ state). The device will
enter D3_HOT. Device behavior in this state is described in Section 3.7.4.4, "The D3HOT State," on
page 78.
On detection of an enabled wakeup frame, the device will assert the nPME signal. The nPME signal
will remain asserted until the PME Enable (PME_EN) and/or the PME Status (PME_STATUS) bits are
cleared by the Host.
Note: If waking from a reduced-power state causes the assertion of a device reset, bit 4 of the Power
Management Control Register (PMT_CTRL) register (WUPS[1]) will be cleared.
Enabling Link Status Change (Energy Detect) Wake Events
The Host system must perform the following steps to enable LAN9420/LAN9420i to assert a PCI wake
event (nPME) on detection of an Ethernet link status change.
1. All transmit and receive operations must be halted:
a. All pending Ethernet TX and RX operations must be completed, and then the DMA controller and
MAC must be halted.
b. The software application must wait for all pending DMA transactions to complete. Upon completion,
no further transactions are permitted.
2. The ENERGYON event must be enabled as a PHY interrupt source. This is done by setting bit 7
in the PHY’s Interrupt Mask register.
3. The PHY must be enabled for the energy detect power down mode. This is done by setting the
EDPWRDOWN bit in the PHY’s Mode Control/Status register. Enabling the energy detect power-
down mode places the PHY in a reduced power state. In this mode of operation the PHY is not
capable of receiving or transmitting Ethernet data. In this state the PHY will assert its internal
interrupt if it detects Ethernet activity. Refer to Section 3.6.8.2, "Energy Detect Power-Down," on
page 74 for more information.
Revision 1.6 (07-18-11)
82
DATASHEET
SMSC LAN9420/LAN9420i