LAN9420 Datasheet, PDF (54/171 Pages) SMSC Corporation – Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface

Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface
Datasheet
3.5.1
3.5.1.1
The MAC block includes a MAC Interface Layer (MIL). The MIL provides a FIFO interface between the
DMAC and the MAC. The MIL provides the following features:
„ Provides a bridge between the DMA controller and Ethernet MAC
„ Separate paths for transmit and receive operations
„ Separate 2KB FIFOs (one for Transmit and one for Receive operations)
„ Receive: Sends only filtered packets to DMAC
„ Transmit: Supports Store and Forward mechanism
„ Transmit: Frame data held in MIL FIFO until the MAC retransmits the packets without collision
The MAC incorporates the essential protocol requirements for operating an Ethernet/IEEE 802.3-
compliant node and provides an interface between the Host system and the internal Ethernet PHY.
The MAC can operate in either 100-Mbps or 10-Mbps mode.
The MAC operates in both half-duplex and full-duplex modes. When operating in half-duplex mode,
the MAC complies fully with Section 4 of ISO/IEC 8802-3 (ANSI/IEEE standard) and ANSI/IEEE 802.3
standards. When operating in full-duplex mode, the MAC complies with IEEE 802.3x full-duplex
operation standard.
The MAC provides programmable enhanced features designed to minimize Host supervision, bus
utilization, and pre- or post-message processing. These features include the ability to disable retries
after a collision, dynamic FCS (Frame Check Sequence) generation on a frame-by-frame basis,
automatic pad field insertion and deletion to enforce minimum frame size attributes, and automatic
retransmission and detection of collision frames, as well as an L3 checksum offload engine for transmit
and receive operations.
The MAC can sustain transmission or reception of minimally-sized back-to-back packets at full line
speed with an inter-packet gap (IPG) of 9.6 microseconds for 10 Mbps and 0.96 microseconds for 100
Mbps.
The transmit and receive data paths are separate within the MAC, allowing the highest performance,
especially in full duplex mode.
The MAC includes a control and status register block (MCSR) through which the MAC can be
configured and monitored by the Host. The MCSR are accessible from the Host system via the Target
Interface of the PCIB.
On the backend, the MAC interfaces with the 10/100 PHY through an MII (Media Independent
Interface) port which is internal to LAN9420/LAN9420i. The MCSR also provide a mechanism for
accessing the PHY’s internal registers through the internal SMI (Serial Management Interface) bus.
Flow Control
The MAC supports full-duplex flow control using the pause operation and control frame.
Full-Duplex Flow Control
The pause operation inhibits data transmission of data frames for a specified period of time. A pause
operation consists of a frame containing the globally assigned multicast address (01-80-C2-00-00-01),
the PAUSE opcode, and a parameter indicating the quantum of slot time (512 bit times) to inhibit data
transmissions. The PAUSE parameter may range from 0 to 65,535 slot times. The Ethernet MAC logic,
on receiving a frame with the reserved multicast address and PAUSE opcode, inhibits data frame
transmissions for the length of time indicated. If a pause request is received while a transmission is in
progress, then the pause will take effect after the transmission is complete. Control frames are received
and processed by the MAC and are passed on.
The MAC also transmits control frames (pause command) under software control. The software driver
requests the MAC to transmit a control frame, and gives the value of the PAUSE time to be used in
the control frame, through the MAC’s FLOW register. The MAC constructs a control frame with the
Revision 1.6 (07-18-11)
54
DATASHEET
SMSC LAN9420/LAN9420i