LAN9420 Datasheet, PDF (52/171 Pages) SMSC Corporation – Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface

3.4.8
3.4.9
3.4.9.1
3.4.10
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface
Datasheet
Poll Demand (for example, a buffer is available before the next incoming frame) and enter the running
state.
Stopping Transmission and Reception
The receive and transmit processes and paths are independent of each other. One does not need to
be stopped as a result of stopping the other. However, the sequence of operations required to stop
elements in the receive path must be explicitly followed, in order to preclude unexpected results and
untoward operation.
In order to stop the transmission, the TX DMAC should be stopped before the MAC’s transmitter (Clear
bit 13 (ST) of DMAC_CONTROL to stop TX DMA, then clear bit 3 (TXEN) of MAC_CR to turn the
transmitter off).
In order to stop reception, the MAC’s receiver should be stopped prior to stopping the RX DMAC (Clear
bit 2 (RXEN) of MAC_CR to turn the receiver off, then clear bit 1 (SR) of DMAC_CONTROL to stop
RX DMA). Performing these steps in the reverse order will result in RX DMA not stopping
(DMAC_STATUS will continue to show the Receive Process State (RS) as Running and Receive
Process Stopped (RPS) does not assert).
TX Buffer Fragmentation Rules
Transmit buffers must adhere to the following rules:
„ Each buffer can start and end on any arbitrary byte alignment
„ The first buffer of any transmit packet can be any length
„ Middle buffers (i.e., those with First Segment = Last Segment = 0) must be greater than, or equal
to 4 bytes in length
„ The final buffer of any transmit packet can be any length
Additionally, the MIL operates in store-and-forward mode and has specific rules with respect to
fragmented packets. The total space consumed in the TX FIFO (MIL) must be limited to no more than
2KB - 3 DWORDs (2,036 bytes total). Any transmit packet that is so highly fragmented that it takes
more space than this must be un-fragmented (by copying to a driver-supplied buffer) before the
transmit packet can be sent to LAN9420/LAN9420i.
One approach to determine whether a packet is too fragmented is to calculate the actual amount of
space that it will consume, and check it against 2,036 bytes. Another approach is to check the number
of buffers against a worst-case limit of 86 (see explanation below).
Calculating Worst-Case TX FIFO (MIL) Usage
The actual space consumed by a buffer in the MIL TX FIFO consists of any partial DWORD offsets in
the first/last DWORD of the buffer, plus all of the whole DWORDs in between. The worst-case
overhead for a TX buffer is 6 bytes, which assumes that it started on the high byte of a DWORD and
ended on the low byte of a DWORD. A TX packet consisting of 86 such fragments would have an
overhead of 516 bytes (6 * 86) which, when added to a 1514-byte max-size transmit packet (1516
bytes, rounded up to the next whole DWORD), would give a total space consumption of 2,032 bytes,
leaving 4 bytes to spare; this is the basis for the "86 fragment" rule mentioned above.
DMAC Interrupts
As described in earlier sections, there are numerous events that cause a DMAC interrupt. The
DMAC_STATUS register contains all the bits that might cause an interrupt. The DMAC_INTR_ENA
register contains an enable bit for each of the events that can cause a DMAC interrupt. The DMAC
interrupt to the Interrupt Controller is asserted if any of the enabled interrupt conditions are satisfied.
There are two groups of interrupts: normal and abnormal (as outlined in DMAC_STATUS). Interrupts
are cleared by writing a logic 1 to the bit. When all the enabled interrupts within a group are cleared,
Revision 1.6 (07-18-11)
52
DATASHEET
SMSC LAN9420/LAN9420i