LAN9420 Datasheet, PDF (68/171 Pages) SMSC Corporation – Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface

Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface
Datasheet
MAC
RX_CLK
100M
PLL
Internal
MII 25MHz by 4 bits
MII
NRZI
MLT-3
Converter ^{NRZI Converter}
25MHz
by 4 bits
4B/5B 25MHz by Descrambler
Decoder
5 bits
and SIPO
125 Mbps Serial
MLT-3
DSP: Timing
recovery, Equalizer
and BLW Correction
A/D
Converter
MLT-3
Magnetics
MLT-3
RJ45
MLT-3 CAT-5
3.6.2
3.6.2.1
3.6.2.2
3.6.2.3
6 bit Data
Figure 3.26 Receive Data Path
100BASE-TX Receive
The receive data path is shown in Figure 3.26. Detailed descriptions follow.
100M Receive Input
The MLT-3 from the cable is fed into the PHY (on inputs TPI+ and TPI-) via a 1:1 ratio transformer.
The ADC samples the incoming differential signal at a rate of 125M samples per second. Using a 64-
level quanitizer it generates 6 digital bits to represent each sample. The DSP adjusts the gain of the
ADC according to the observed signal levels such that the full dynamic range of the ADC can be used.
Equalizer, Baseline Wander Correction and Clock and Data Recovery
The 6 bits from the ADC are fed into the DSP block. The equalizer in the DSP section compensates
for phase and amplitude distortion caused by the physical channel consisting of magnetics, connectors,
and CAT- 5 cable. The equalizer can restore the signal for any good-quality CAT-5 cable between 1m
and 150m.
If the DC content of the signal is such that the low-frequency components fall below the low frequency
pole of the isolation transformer, then the droop characteristics of the transformer will become
significant and Baseline Wander (BLW) on the received signal will result. To prevent corruption of the
received data, the PHY corrects for BLW and can receive the ANSI X3.263-1995 FDDI TP-PMD
defined “killer packet” with no bit errors.
The 100M PLL generates multiple phases of the 125MHz clock. A multiplexer, controlled by the timing
unit of the DSP, selects the optimum phase for sampling the data. This is used as the received
recovered clock. This clock is used to extract the serial data from the received signal.
NRZI and MLT-3 Decoding
The DSP generates the MLT-3 recovered levels that are fed to the MLT-3 converter. The MLT-3 is then
converted to an NRZI data stream.
Revision 1.6 (07-18-11)
68
DATASHEET
SMSC LAN9420/LAN9420i