LAN9420 Datasheet, PDF(63/171 Page) SMSC Corporation – Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface

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LAN9420 Datasheet, PDF (63/171 Pages) SMSC Corporation – Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface

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Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface

Datasheet

3.5.5.1

3.5.6

The RXCOE resides in the RX path within the MAC. As the RXCOE receives an Ethernet frame it

calculates the 16-bit checksum. The RXCOE passes the Ethernet frame to the DMAC with the

checksum appended to the end of the frame. The RXCOE inserts the checksum immediately after the

last byte of the Ethernet frame. The frame length field (FL) of receive descriptor 0 (RDES0) indicates

that the frame size is increased by two bytes to accommodate the checksum.

Setting the RX_COE_EN bit in the Checksum Offload Engine Control Register (COE_CR) enables the

RXCOE, while the RX_COE_MODE bit selects the operating mode. When the RXCOE is disabled, the

received data is simply passed through the RXCOE unmodified.

Note: Software applications must stop the receiver and flush the RX data path before changing the

state of the RX_COE_EN or RX_COE_MODE bits.

Note: When the RXCOE is enabled, automatic pad stripping must be disabled (PADSTR bit of the

MAC Control Register (MAC_CR)) and vice versa. These functions cannot be enabled

simultaneously.

RX Checksum Calculation

The checksum is calculated 16 bits at a time. In the case of an odd sized frame, an extra byte of zero

is used to pad up to 16 bits.

Consider the following packet: DA, SA, Type, B0, B1, B2 â¦ BN, FCS

Let [A, B] = A*256 + B;

If the packet has an even number of octets then

checksum = [B1, B0] + C0 + [B3, B2] + C1 + â¦ + [BN, BN-1] + CN-1

Where C0, C1, ... CN-1 are the carry out results of the intermediate sums.

If the packet has an odd number of octets then

checksum = [B1, B0] + C0 + [B3, B2] + C1 + â¦ + [0, BN] + CN-1

Transmit Checksum Offload Engine (TXCOE)

The transmit checksum offload engine (TXCOE) provides assistance to the Host by calculating a 16-

bit checksum, typically for TCP, for a transmit Ethernet frame. The TXCOE calculates the checksum

and inserts the results back into the data stream as it is transferred to the MAC.

When bit 27 of TDES1 (CK bit) is set in conjunction with bit 29 of TDES1 (FS bit) and bit 16 of the

COE_CR register (TX_COE_EN), the TXCOE will perform a checksum calculation on the associated

packet. When these three bits are set, a 32-bit TX checksum preamble must be pre-pended to the

beginning of the TX packet (refer to Table 3.20). The TX checksum preamble instructs the TXCOE on

the handling of the associated packet. Bits 11:0 of the TX checksum preamble define the byte offset

at which the data checksum calculation will begin. The checksum calculation will begin at this offset

and will continue until the end of the packet. The data checksum calculation must not begin in the MAC

header (first 14 bytes) or in the last 4 bytes of the TX packet. When the calculation is complete, the

checksum will be inserted into the packet at the byte offset defined by bits 27:16 of the TX checksum

preamble. The TX checksum cannot be inserted in the MAC header (first 14 bytes) or in the last 4

bytes of the TX packet.

If the TX packet already includes a partial checksum calculation (perhaps inserted by an upper layer

protocol), this checksum can be included in the hardware checksum calculation by setting the TXCSSP

field in the TX checksum preamble to include the partial checksum. The partial checksum can be

replaced by the completed checksum calculation by setting the TXCSLOC pointer to point to the

location of the partial checksum.

SMSC LAN9420/LAN9420i

DATASHEET

Revision 1.6 (07-18-11)

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