LAN9420 Datasheet, PDF (64/171 Pages) SMSC Corporation – Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface

Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface
Datasheet
Note: The TXCOE_MODE may only be changed if the TX path is disabled. If it is desired to change
this value during run time, it is safe to do so only after the DMA is disabled and the MIL is
empty.
Note: The TX checksum preamble must be DWORD-aligned.
BITS
31:28
27:16
15:12
11:0
Table 3.20 TX Checksum Preamble
DESCRIPTION
RESERVED
TXCSLOC - TX Checksum Location
This field specifies the byte offset where the TX checksum will be inserted in the TX packet. The
checksum will replace two bytes of data starting at this offset.
Note: The TX checksum cannot be inserted in the MAC header (first 14 bytes) or in the last 4
bytes of the TX packet.
RESERVED
TXCSSP - TX Checksum Start Pointer
This field indicates start offset, in bytes, where the checksum calculation will begin in the associated
TX packet.
Note: The data checksum calculation must not begin in the MAC header (first 14 bytes) or in
the last 4 bytes of the TX packet.
3.5.6.1
3.5.7
TX Checksum Calculation
The TX checksum calculation is performed using the same operation as the RX checksum, with the
exception that the calculation starts as indicated by the preamble, and the transmitted checksum is the
one’s-compliment of the final calculation.
Note:
When the TX checksum offload feature is invoked, if the calculated checksum is 0000h, it is
left unaltered. UDP checksums are optional under IPv4, and a zero checksum calculated by
the TX checksum offload feature will erroneously indicate to the receiver that no checksum was
calculated, however, the packet will typically not be rejected by the receiver. Under IPv6,
however, according to RFC 2460, the UDP checksum is not optional. A calculated checksum
that yields a result of zero must be changed to FFFFh for insertion into the UDP header. IPv6
receivers discard UDP packets containing a zero checksum. Thus, this feature must not be
used for UDP checksum calculation under IPv6.
MAC Control and Status Registers (MCSR)
Please refer to Section 4.4, "MAC Control and Status Registers (MCSR)," on page 119 for a complete
description of the MCSR.
3.6
10/100 Ethernet PHY
LAN9420/LAN9420i integrates an IEEE 802.3 Physical Layer for Twisted Pair Ethernet applications
(PHY). The PHY can be configured for either 100 Mbps (100BASE-TX) or 10 Mbps (10BASE-T)
Ethernet operation.
The PHY block includes:
„ Support for auto-negotiation
„ Automatic polarity detection and correction
„ HP Auto-MDIX
Revision 1.6 (07-18-11)
64
DATASHEET
SMSC LAN9420/LAN9420i