LAN9420 Datasheet, PDF (29/171 Pages) SMSC Corporation – Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface

Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface
Datasheet
„ General-purpose timer interrupt (GPT_INT)
„ General purpose Input/Output interrupt (GPIOx_INT)
„ Software interrupt (SW_INT)
„ Master bus error interrupt (MBERR_INT)
„ Slave bus error interrupt (SBERR_INT)
„ Wake event detection (WAKE_INT)
A Block diagram of the Interrupt Controller is shown in Figure 3.6.
.
Interrupt Controller
SW_INT_EN
RW
(INT_CTL Register)
0 to 1
DETECT
SW_INT
(INT_STS Register)
Master Bus Error
Interrupt
Slave Bus Error
Interrupt
GPIO2 Interrupt
GPIO1 Interrupt
GPIO0 Interrupt
GP Timer Interrupt
MBERR_INT
(INT_STS Register)
MBERR_INT_EN
(INT_CTL Register) ^RW
SBERR_INT
(INT_STS Register)
SBERR_INT_EN
(INT_CTL Register) ^RW
GPIO2_INT
(INT_STS Register)
GPIO2_INT_EN
(INT_CTL Register) ^RW
GPIO1_INT
(INT_STS Register)
GPIO1_INT_EN
(INT_CTL Register) ^RW
GPIO0_INT
(INT_STS Register)
GPIO0_INT_EN
(INT_CTL Register) ^RW
GPT_INT
(INT_STS Register)
GPT_INT_EN
(INT_CTL Register) ^RW
PHY Interrupt
PHY_INT_EN
(INT_CTL Register) ^RW
DMAC Interrupt
PHY_INT
RO _{(INT_STS Register)}
DMAC_INT
RO _{(INT_STS Register)}
INT_DEAS[7:0]
(INT_CFG Register) ^RW
INT_DEAS_CLR
(INT_CFG Register) ^RW
Wake Event Interrupt
WAKE_INT_EN
(INT_CTL Register) ^RW
WAKE_INT
RO _{(INT_STS Register)}
DEASSERTION
TIMER
INT_DEAS_STS
RO _{(INT_CFG Register)}
IRQ_EN
(INT_CTL Register) ^RW
IRQ_INT
(INT_CFG Register)
RO
IRQ
(PCIB)
Figure 3.6 Interrupt Controller Block Diagram
The Interrupt Controller control and status register are contained within the System Control and Status
Registers (SCSR) block. The interrupt status register (INT_STS) reflects the current state of the
interrupt sources prior to qualification with their associated enables. The SW_INT, MBERR_INT,
SBERR_INT, GPIOx_INT, and GPT_INT are latched, and are cleared through the SCSR block upon a
SMSC LAN9420/LAN9420i
29
DATASHEET
Revision 1.6 (07-18-11)