LAN9420 Datasheet, PDF (116/171 Pages) SMSC Corporation – Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface

4.3.9
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface
Datasheet
Missed Frame and Buffer Overflow Counter Reg (MISS_FRAME_CNTR)
Offset:
0020h
Size:
32 bits
The DMAC maintains two counters to track the number of missed frames during a receive operation.
The MISS_FRAME_CNTR register reports the current value of these counters and their overflow bits.
BITS
31:29
28
27:17
16
15:0
DESCRIPTION
RESERVED
MIL RX FIFO Full Counter Overflow (MIL_OVER)
Overflow bit for the MIL_FIFO_FULL counter. This bit is automatically
cleared on a read.
MIL RX FIFO Full Counter (MIL_FIFO_FULL)
This field indicates the number of frames missed due a MIL RX FIFO full
condition. This counter is automatically cleared on a read.
RX Buffer Unavailable Counter Overflow (UNAV_OVER)
Overflow bit for the RX_BUFF_UNAV counter. This bit is automatically
cleared on a read.
RX Buffer Unavailable Counter (RX_BUFF_UNAV)
This field indicates the number of frames missed due to receive buffers
being unavailable. This counter is incremented each time the DMAC
discards an incoming frame. This counter is automatically cleared on a
read.
TYPE
RO
RC
RC
RC
RC
DEFAULT
-
0b
000h
0b
0000h
Revision 1.6 (07-18-11)
116
DATASHEET
SMSC LAN9420/LAN9420i