LAN9420 Datasheet, PDF (114/171 Pages) SMSC Corporation – Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface

4.3.8
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface
Datasheet
DMA Controller Interrupt Enable Register (DMAC_INTR_ENA)
Offset:
001Ch
Size:
32 bits
This register enables the DMAC interrupts reported in the DMAC_STATUS register. Setting a bit to 1
enables the corresponding interrupt. After a hardware or software reset, all interrupts are disabled.
BITS
31:17
16
DESCRIPTION
RESERVED
Normal Interrupt Summary Enable (NIS_EN)
When set, normal interrupt is enabled. When reset, no normal interrupt is
enabled. This bit enables the following bits:
DMAC_STATUS[0]: Transmit interrupt (TI)
DMAC_STATUS[2]: Transmit buffer unavailable (TU)
DMAC_STATUS[6]: Receive interrupt (RI)
TYPE
RO
R/W
DEFAULT
-
0b
15 Abnormal Interrupt Summary Enable (AIS_EN)
R/W
0b
When set, abnormal interrupt is enabled. When reset, no abnormal interrupt
is enabled. This bit enables the following bits:
DMAC_STATUS[1]: Transmit process stopped (TPS)
DMAC_STATUS[5]: RESERVED
DMAC_STATUS[7]: Receive buffer unavailable (RU)
DMAC_STATUS[8]: Receive process stopped (RPS)
14 RESERVED
R/W
0b
13:11
10
RESERVED
RESERVED
RO
-
R/W
0b
9
Receive Watchdog Timeout (RWT_EN)
R/W
0b
The Receive Watchdog Timeout is enabled only when this bit and the
Abnormal Interrupt Summary Enable bit (bit [15]) are set.
8
Receive Process Stopped (RPS_EN)
R/W
0b
The Receive Process Stopped Interrupt is enabled only when this bit and
the Abnormal Interrupt Summary Enable bit (bit [15]) are set.
7
Receive Buffer Unavailable (RU_EN)
R/W
0b
The Receive Buffer Unavailable Interrupt is enabled only when this bit and
the Abnormal Interrupt Summary Enable bit (bit [15]) are set.
6
Receive Interrupt (RI_EN)
R/W
0b
The Receive Interrupt is enabled only when this bit and the Abnormal
Interrupt Summary Enable bit (bit [15]) are set.
5
RESERVED
R/W
0b
4:3 RESERVED
RO
-
2
Transmit Buffer Unavailable (TU_EN)
R/W
0b
The Transmit Buffer Unavailable Interrupt is enabled only when this bit and
the Normal Interrupt Summary Enable bit (bit [16]) are set.
Revision 1.6 (07-18-11)
114
DATASHEET
SMSC LAN9420/LAN9420i