LAN9420 Datasheet, PDF (78/171 Pages) SMSC Corporation – Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface

Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface
Datasheet
3.7.4.3.2
3.7.4.4
3.7.4.4.1
3.7.4.4.2
EXITING THE D0_A STATE
The device will exit the D0_A state under the following conditions. State transitions are illustrated in
Figure 3.28 on page 76.
„ D0_A to D3_HOT (T3): This transition occurs when, during normal device operation, the Host system
selects the “D3” state in the Power Management State (PM_STATE) field of the PCI Power
Management Control and Status Register (PCI_PMCSR). (PCInRST=1, PM_STATE=00b to 11b,
VAUXDET=X, PWRGOOD=1). If the PME Enable (PME_EN) bit in the PCI Power Management
Control and Status Register (PCI_PMCSR) is cleared, the internal PHY is reset and is placed in
the General Power-Down mode on this transition. If PME Enable (PME_EN) is set, it is assumed
that the device will be required to detect Ethernet power management events and the PHY is not
reset or placed in General Power-Down mode.
„ D0_A to D0_U (T7): This transition occurs when PCInRST is asserted while in the D0_A state
(PCInRST=1 to 0, PM_STATE=00b, VAUXDET=X, PWRGOOD=1).
„ D0_A to D3_COLD (T11): This transition occurs when all power supplies are operational and the device
has been initialized and the Power Management State (PM_STATE) field of the PCI Power
Management Control and Status Register (PCI_PMCSR) is set to “D0”, and then PCI power is
turned off and 3.3Vaux is still operational (PCInRST=1, PM_STATE=00b, VAUXDET=1,
PWRGOOD=1 to 0).The internal PHY is reset and is placed in the General Power-Down mode on
this transition. Note that if VAUXDET=0, the device is being powered from the PCI +3.3V supply
and will turn off (G3) when PCI power is removed.
„ D0_A to G3 (T12): This transition occurs when all power supplies are turned off (PCInRST=X,
PM_STATE=XXb, VAUXDET=1 to 0, PWRGOOD=1 to 0). For example, total power failure.
The D3_HOT State
In this state the PCI power is on, but normal Ethernet receive and transmit operation is disabled. In
D3_HOT power is reduced by disabling the internal PLL and derivative clocks. If the PME Enable
(PME_EN) bit in the PCI Power Management Control and Status Register (PCI_PMCSR) is cleared,
power is also conserved by placing the internal PHY into General Power-Down mode on transition to
this state.
In D3_HOT PCI configuration accesses are permitted, but the device will not respond to PCI memory or
I/O accesses. While in this state, the Power Management State (PM_STATE) field of the PCI Power
Management Control and Status Register (PCI_PMCSR) will indicate a setting of 11b (D3 state).
POWER MANAGEMENT EVENTS IN D3_HOT
If configured to do so, the device is capable of detecting MAC (WOL, Magic Packet) and PHY (link
status change) wake events and is capable of asserting nPME as a result of detection. Refer to section
Section 3.7.6, "Detecting Power Management Events," on page 81 for more information.
EXITING THE D3_HOT STATE
The device will exit the D3_HOT state under the following conditions. State transitions are illustrated in
Figure 3.28 on page 76.
„ D3_HOT to D3_COLD (T4): This transition occurs after the device has been placed in the D3_HOT state
by the Host system and then PCI power is turned off, but PCI 3.3Vaux remains operational
(PCInRST=X, PM_STATE=11b, VAUXDET=1, PWRGOOD=1 to 0). In this state the device is
powered by the PCI 3.3Vaux supply.
„ D3_HOT to D0_U (T5): This transition occurs when the device is in the D3_HOT state and Host system
selects the “D0” state in the Power Management State (PM_STATE) field of the PCI Power
Management Control and Status Register (PCI_PMCSR) (PCInRST=1, PM_STATE=11b to 00b,
VAUXDET=X, PWRGOOD=1). A D3 Transition Reset (D3RST) occurs during this transition. Refer
to Section 3.7.5, "Resets," on page 79 to for more information on this reset.
Revision 1.6 (07-18-11)
78
DATASHEET
SMSC LAN9420/LAN9420i