LAN9420 Datasheet, PDF (111/171 Pages) SMSC Corporation – Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface

Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface
Datasheet
BITS
15
DESCRIPTION
Abnormal Interrupt Summary (AIS)
This bit is the logical OR of other bits within this register. Only unmasked
bits affect this register. Below is the list of bits:
DMAC_STATUS[1]: Transmit process stopped (TPS)
DMAC_STATUS[7]: Receive buffer unavailable (RU)
DMAC_STATUS[8]: Receive process stopped (RPS)
TYPE
R/WC
14:10
9
8
7
6
5:3
2
1
0
RESERVED
Receive Watchdog Timeout (RWT)
A Receive Watchdog Timeout occurs when the length of the receiving frame
is greater than 2048 bytes through 2560 bytes.
Receive Process Stopped (RPS)
Asserted when the Receive process enters the stopped state.
Receive Buffer Unavailable (RU)
Indicates that the next descriptor in the receive list is owned by the Host
and cannot be acquired by the DMA Controller. The reception process is
suspended. To resume processing receive descriptors, the Host should
change the ownership of the descriptor and issue a receive poll demand
command. If no receive poll demand is issued, the reception process
resumes when the next recognized incoming frame is received.
After the first assertion, RU is not asserted for any subsequent “not owned”
receive descriptor fetches. RU is set only when the previous receive
descriptor was owned by the DMA controller. RU remains asserted until it
is cleared by software.
Receive Interrupt (RI)
Indicates the completion of the frame reception. Specific frame status
information has been posted in the descriptor. The reception process
remains in the running state.
RESERVED
Transmit Buffer Unavailable (TU)
Indicates that the next descriptor in the Transmit list is owned by the Host
system and cannot be acquired by the DMA Controller. The transmission
process is suspended (bits [22:20]). To resume processing transmit
descriptors, the Ownership bit in the descriptor should be set, indicating that
the DMA Controller now owns the buffer and then a transmit poll demand
command should be issued.
Transmit Process Stopped (TPS)
Set when the transmit process enters the stopped state.
Transmit Interrupt (TI)
Indicates that a frame transmission was completed and TDES1[31] is set in
the first Descriptor indicating that the TX descriptor has been updated.
RO
R/WC
R/WC
R/WC
R/WC
RO
R/WC
R/WC
R/WC
DEFAULT
0b
-
0b
0b
0b
0b
-
0b
0b
0b
SMSC LAN9420/LAN9420i
111
DATASHEET
Revision 1.6 (07-18-11)