LAN9420 Datasheet, PDF (150/171 Pages) SMSC Corporation – Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface

4.6
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface
Datasheet
PCI Configuration Space CSR (CONFIG CSR)
Configuration and read back of the CONFIG CSR is accomplished by the Host processor via the PCI
bus. These registers assume their default value on assertion of a chip-level reset or when the device
power state transitions from D3 to D0. See Section 3.7, "Power Management," on page 74 for details.
Registers in offsets 00h - 03Fh are standard PCI header registers, as described in the PCI Local Bus
Specification Revision 3.0. Please refer to the specification for further details.
Register 78h is a PCIB specific extension related to power management.
The following is the register map for the PCI Configuration Space CSR (CONFIG CSR):
Table 4.9 PCI Configuration Space CSR (CONFIG CSR) Address Map
CONFIGURATION
SPACE
OFFSET
REGISTER NAME
00h – 3Fh
-
40h – 74h
78h
7Ch
RESERVED
PCI_PMC
PCI_PMCSR
DESCRIPTION
Standard PCI Header Registers (See Table 4.10 on page 151
for details).
PCI Power Management Capabilities Register (PCI_PMC)
PCI Power Management Control and Status Register
(PCI_PMCSR)
Revision 1.6 (07-18-11)
150
DATASHEET
SMSC LAN9420/LAN9420i