LAN9420 Datasheet, PDF (75/171 Pages) SMSC Corporation – Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface

Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface
Datasheet
3.7.2
3.7.3
As a result of the nPME assertion by the device, the PCI Host can reconfigure the power management
state. This mechanism is used, for example, when LAN9420/LAN9420i is in low power mode and must
be restored to a functional state, as a result of the detection of “Wake On LAN” event. The Host can
respond to the subsequent nPME assertion by changing the Power Management State (PM_STATE)
bits in the PCI Power Management Control and Status Register (PCI_PMCSR) to restore
LAN9420/LAN9420i to the D0 state.
As a single function device, LAN9420/LAN9420i implements a PCI Power Management Capabilities
Register (PCI_PMC) and a PCI Power Management Control and Status Register (PCI_PMCSR), which
are mapped into the PCI configuration space at addresses 78h and 7Ch, respectively. The 3.3Vaux
Power Supply Current Draw (AUX_CURRENT) field of the PCI_PMC register is dependant on the
setting of the external VAUXDET pin. The Data_Scale and Data_Select fields of the PCI_PMCSR
register will always return zero, as the Data Register is not implemented.
LAN9420/LAN9420i complies with Revision 1.1 of the PCI Bus Power Management Interface
Specification, V2.0 of the Network Device Class Specification and Revision 3.0 of the Advanced
Configuration and Power Interface Specification (ACPI specification).
Refer to Section 5.3, "Power Consumption," on page 157 for power consumption in the various power
management states.
Related External Signals and Power Supplies
The following external signals are provided in support of PCI power management:
„ nPME: LAN9420/LAN9420i can assert this signal upon detection of an enabled power management
event.
Note: The nPME signal requires external isolation if the system supports wake from B3 and the
LAN9420/LAN9420i’s VAUXDET=0 (i.e., the system is powered, but LAN9420/LAN9420i is not)
„ VAUXDET: This signal enables LAN9420/LAN9420i’s ability to detect power management events
and assert nPME from the D3_COLD state (wake from D3_COLD). When tied to the PCI system’s
3.3Vaux power supply, wake from D3_COLD is enabled. When tied to ground, wake from D3_COLD is
disabled.
„ PWRGOOD: If VAUXDET is low (wake from D3_COLD is disabled) PWRGOOD must be tied to +3.3V
power. If VAUXDET is connected to 3.3Vaux (wake from D3_COLD is enabled), LAN9420/LAN9420i
uses PWRGOOD to determine the state of the system’s +3.3V power supply. When VAUXDET is
high, the device is isolated from the PCI bus when PWRGOOD is deasserted and will ignore all
PCI transactions, including PCICLK and PCInRST.
LAN9420/LAN9420i requires the following external 3.3V power supplies:
„ VDD33IO, VDD33A, VDD33BIAS
The connection of the device’s 3.3V power pins varies depending on the requirement for support of
wake from D3_COLD. If wake from D3_COLD is enabled (VAUXDET is connected to 3.3Vaux), the 3.3V
power pins must be connected to the PCI system’s 3.3Vaux power supply. If wake from D3_COLD is
disabled, (VAUXDET is connected to VSS), the 3.3V power pins must be connected to the system’s
+3.3V power. Please refer to Chapter 2, "Pin Description and Configuration," on page 15 for more
information on the LAN9420/LAN9420i power supplies.
Note: The LAN9420/LAN9420i device also requires 1.8V, but this is supplied by an internal regulator
and connection does not vary. Since the 1.8V supply is derived from VDD33IO, there is no
need to discuss it separately.
Device Clocking
LAN9420/LAN9420i requires a fixed-frequency 25MHz clock source. This is typically provided by
attaching a 25MHz crystal to the XI and XO pins. The clock can optionally be provided by driving the
SMSC LAN9420/LAN9420i
75
DATASHEET
Revision 1.6 (07-18-11)