LAN9420 Datasheet, PDF (170/171 Pages) SMSC Corporation – Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface

Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface
Datasheet
Chapter 7 Datasheet Revision History
Table 7.1 Customer Revision History
REVISION LEVEL & DATE SECTION/FIGURE/ENTRY
CORRECTION
Rev. 1.6
(07-18-11)
Section 3.5.6.1, "TX
Checksum Calculation"
Added note stating TX Checksum calculation
should not be used for UDP packets under IPv6.
Rev. 1.5
(04-12-11)
Section 3.7.7, "Enabling
Link Status Change (Energy
Detect) Wake Events," on
page 82
Step #2 corrected from “This is done by setting the
INT7 bit in the PHY’s Interrupt Source Flag
register.” to “This is done by setting bit 7 in the
PHY’s Interrupt Mask register.”
Section 4.3.1, "Bus Mode
Register (BUS_MODE)," on
page 105
Added note to PBL field description:
“PCI bursts are always 16 cycles, regardless of the
value in this field.”
Rev. 1.4
All
(12-17-08)
Fixed various typos.
Section 3.7.7, "Enabling
Link Status Change (Energy
Detect) Wake Events," on
page 82
Corrected second sentence of step 3: “This is done
by setting the EDPWRDOWN bit in the PHY’s
Mode Control/Status register.”
Section 4.3.1, "Bus Mode
Register (BUS_MODE)," on
page 105
Added DBO and BLE bit definitions.
Table 5.13,
Updated max ESR value to 50 Ohms.
“LAN9420/LAN9420i Crystal
Specifications,” on page 167
Rev. 1.22
(09-23-08)
Added PCI SIG certification logo to cover
Rev. 1.21
(07-30-08)
Figure 1.2
LAN9420/LAN9420i Internal
Block Diagram on page 11
Fixed error: Changed “To option..” text to
“(optional)” and moved it to the end of the
descriptions.
Figure 1.2
LAN9420/LAN9420i Internal
Block Diagram on page 11
- Changed “To option..” text to “(optional)” and
moved it to the end of the descriptions.
- Removed “To” from “To Ethernet”.
- Placed bi-directional arrows on EEPROM,
GPIO/LED, and PHY blocks.
Section 4.5.5, "Auto
Negotiation Advertisement,"
on page 141
Changed bits 9 and 15 to RESERVED with a
default value of 0b.
Table 4.10, “Standard PCI
Header Registers
Supported,” on page 151
Added note to default value of Revision ID stating
that the default value is dependent on device
revision.
Table 4.10, “Standard PCI
Header Registers
Supported,” on page 151
Changed default values of Min_Gnt and Max_Lat
to 02h and 04h, respectively.
Section 3.5.5.1, "RX
Checksum Calculation," on
page 63
Changed last line of RX checksum calculation to
“checksum = [B1, B0] + C0 + [B3, B2] + C1 + …
+ [0, BN] + CN-1”
Revision 1.6 (07-18-11)
170
DATASHEET
SMSC LAN9420/LAN9420i