C8051F70X_0910 Datasheet, PDF (99/290 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F70x/71x
SFR Definition 16.2. EMI0CF: External Memory Configuration
Bit
7
6
5
4
3
2
1
0
Name
EMD2
EMD[1:0]
EALE[1:0]
Type
R
R/W
Reset
0
0
0
0
0
0
1
1
SFR Address = 0xC7; SFR Page = F
Bit Name
Function
7:5 Unused Read = 000b; Write = Don’t Care.
4
EMD2 EMIF Multiplex Mode Select Bit.
0: EMIF operates in multiplexed address/data mode
1: EMIF operates in non-multiplexed mode (separate address and data pins)
3:2 EMD[1:0] EMIF Operating Mode Select Bits.
00: Internal Only: MOVX accesses on-chip XRAM only. All effective addresses alias to
on-chip memory space
01: Split Mode without Bank Select: Accesses below the 256 B boundary are directed
on-chip. Accesses above the 256 B boundary are directed off-chip. 8-bit off-chip MOVX
operations use current contents of the Address high port latches to resolve the upper
address byte. To access off chip space, EMI0CN must be set to a page that is not con-
tained in the on-chip address space.
10: Split Mode with Bank Select: Accesses below the 256 B boundary are directed on-
chip. Accesses above the 256 B boundary are directed off-chip. 8-bit off-chip MOVX
operations uses the contents of EMI0CN to determine the high-byte of the address.
11: External Only: MOVX accesses off-chip XRAM only. On-chip XRAM is not visible to
the CPU.
1:0 EALE[1:0] ALE Pulse-Width Select Bits.
These bits only have an effect when EMD2 = 0.
00: ALE high and ALE low pulse width = 1 SYSCLK cycle.
01: ALE high and ALE low pulse width = 2 SYSCLK cycles.
10: ALE high and ALE low pulse width = 3 SYSCLK cycles.
11: ALE high and ALE low pulse width = 4 SYSCLK cycles.
Rev. 0.3
99