C8051F70X_0910 Datasheet, PDF (198/290 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F70x/71x
SFR Definition 27.2. CRC0IN: CRC Data Input
Bit
7
6
5
4
3
2
1
0
Name
CRC0IN[7:0]
Type
R/W
Reset
0
0
0
0
0
0
0
0
SFR Address = 0x94; SFR Page = F
Bit
Name
Function
7:0 CRC0IN[7:0] CRC0 Data Input.
Each write to CRC0IN results in the written data being computed into the existing
CRC result according to the CRC algorithm described in Section 27.1
SFR Definition 27.3. CRC0DATA: CRC Data Output
Bit
7
6
5
4
3
2
1
0
Name
CRC0DAT[7:0]
Type
R/W
Reset
0
0
0
0
0
0
0
0
SFR Address = 0xD9; SFR Page = F
Bit
Name
Function
7:0 CRC0DAT[7:0] CRC0 Data Output.
Each read or write performed on CRC0DAT targets the CRC result bits pointed to
by the CRC0 Result Pointer (CRC0PNT bits in CRC0CN).
198
Rev. 0.3