C8051F70X_0910 Datasheet, PDF (9/290 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F70x/71x
14. CIP-51 Microcontroller
Figure 14.1. CIP-51 Block Diagram ......................................................................... 83
15. Memory Organization
Figure 15.1. C8051F70x/71x Memory Map ............................................................. 93
Figure 15.2. Flash Program Memory Map ............................................................... 94
16. External Data Memory Interface and On-Chip XRAM
Figure 16.1. Multiplexed Configuration Example ................................................... 100
Figure 16.2. Non-multiplexed Configuration Example ........................................... 101
Figure 16.3. EMIF Operating Modes ..................................................................... 102
Figure 16.4. Non-multiplexed 16-bit MOVX Timing ............................................... 105
Figure 16.5. Non-multiplexed 8-bit MOVX without Bank Select Timing ................ 106
Figure 16.6. Non-multiplexed 8-bit MOVX with Bank Select Timing ..................... 107
Figure 16.7. Multiplexed 16-bit MOVX Timing ....................................................... 108
Figure 16.8. Multiplexed 8-bit MOVX without Bank Select Timing ........................ 109
Figure 16.9. Multiplexed 8-bit MOVX with Bank Select Timing ............................. 110
17. In-System Device Identification
18. Special Function Registers
19. Interrupts
20. Flash Memory
21. EEPROM
Figure 21.1. EEPROM Block Diagram .................................................................. 140
22. Power Management Modes
23. Reset Sources
Figure 23.1. Reset Sources ................................................................................... 148
Figure 23.2. Power-On and VDD Monitor Reset Timing ....................................... 149
24. Watchdog Timer
25. Oscillators and Clock Selection
Figure 25.1. Oscillator Options .............................................................................. 156
Figure 25.2. External 32.768 kHz Quartz Crystal Oscillator Connection Diagram 163
26. Port Input/Output
Figure 26.1. Port I/O Functional Block Diagram .................................................... 165
Figure 26.2. Port I/O Cell Block Diagram .............................................................. 167
Figure 26.3. Port I/O Overdrive Current ................................................................ 167
Figure 26.4. Crossbar Priority Decoder—Possible Pin Assignments .................... 170
Figure 26.5. Crossbar Priority Decoder Example .................................................. 171
27. Cyclic Redundancy Check Unit (CRC0)
Figure 27.1. CRC0 Block Diagram ........................................................................ 193
28. SMBus
Figure 28.1. SMBus Block Diagram ...................................................................... 201
Figure 28.2. Typical SMBus Configuration ............................................................ 202
Figure 28.3. SMBus Transaction ........................................................................... 203
Figure 28.4. Typical SMBus SCL Generation ........................................................ 205
Figure 28.5. Typical Master Write Sequence ........................................................ 214
Figure 28.6. Typical Master Read Sequence ........................................................ 215
Figure 28.7. Typical Slave Write Sequence .......................................................... 216
Rev. 0.3
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