C8051F70X_0910 Datasheet, PDF (120/290 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F70x/71x
Table 18.2. Special Function Registers (Continued)
SFRs are listed in alphabetical order. All undefined SFR locations are reserved
Register
PCA0CN
PCA0CPH0
PCA0CPH1
PCA0CPH2
PCA0CPL0
PCA0CPL1
PCA0CPL2
PCA0CPM0
PCA0CPM1
PCA0CPM2
PCA0H
PCA0L
PCA0MD
PCA0PWM
PCON
PSCTL
PSW
REF0CN
REG0CN
REVID
RSTSRC
SBUF0
SCON0
SFRPAGE
SMB0ADM
SMB0ADR
SMB0CF
SMB0CN
SMB0DAT
SP
SPI0CFG
SPI0CKR
SPI0CN
SPI0DAT
Address
0xD8
0xFC
0xEA
0xEC
0xFB
0xE9
0xEB
0xDA
0xDB
0xDC
0xFA
0xF9
0xED
0xA1
0x87
0x8F
0xD0
0xD2
0xB9
0xAD
0xEF
0x99
0x98
0xA7
0xBB
0xBA
0xC1
0xC0
0xC2
0x81
0xA1
0xA2
0xF8
0xA3
Page
All Pages
0
0
0
0
0
0
F
F
F
0
0
F
F
All Pages
All Pages
All Pages
F
F
F
All Pages
All Pages
All Pages
All Pages
F
F
0
All Pages
0
All Pages
0
F
All Pages
0
PCA Control
Description
PCA Capture 0 High
PCA Capture 1 High
PCA Capture 2 High
PCA Capture 0 Low
PCA Capture 1 Low
PCA Capture 2 Low
PCA Module 0 Mode Register
PCA Module 1 Mode Register
PCA Module 2 Mode Register
PCA Counter High
PCA Counter Low
PCA Mode
PCA PWM Configuration
Power Control
Program Store R/W Control
Program Status Word
Voltage Reference Control
Voltage Regulator Control
Revision ID
Reset Source Configuration/Status
UART0 Data Buffer
UART0 Control
SFR Page
SMBus Slave Address mask
SMBus Slave Address
SMBus Configuration
SMBus Control
SMBus Data
Stack Pointer
SPI0 Configuration
SPI0 Clock Rate Control
SPI0 Control
SPI0 Data
120
Rev. 0.3
Page
278
283
283
283
283
283
283
281
281
281
282
282
279
280
147
138
92
62
64
114
153
242
241
117
212
211
207
209
213
90
230
232
231
232