C8051F70X_0910 Datasheet, PDF (173/290 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F70x/71x
SFR Definition 26.1. XBR0: Port I/O Crossbar Register 0
Bit
7
Name
Type
R
Reset
0
6
5
4
3
2
1
0
CP0AE
CP0E SYSCKE SMB0E
SPI0E
URT0E
R
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
SFR Address = 0xE1; SFR Page = F
Bit Name
Function
7:6 Unused Read = 00b; Write = Don’t Care.
5 CP0AE _{Comparator0 Asynchronous Output Enable.}
0: Asynchronous CP0 unavailable at Port pin.
1: Asynchronous CP0 routed to Port pin.
4
CP0E _{Comparator0 Output Enable.}
0: CP0 unavailable at Port pin.
1: CP0 routed to Port pin.
3 SYSCKE _{SYSCLK Output Enable.}
0: SYSCLK unavailable at Port pin.
1: SYSCLK output routed to Port pin.
2 SMB0E _{SMBus I/O Enable.}
0: SMBus I/O unavailable at Port pins.
1: SMBus I/O routed to Port pins.
1 SPI0E _{SPI I/O Enable.}
0: SPI I/O unavailable at Port pins.
1: SPI I/O routed to Port pins. Note that the SPI can be assigned either 3 or 4 GPIO
pins.
0 URT0E _{UART I/O Output Enable.}
0: UART I/O unavailable at Port pin.
1: UART TX0, RX0 routed to Port pins P0.4 and P0.5.
Rev. 0.3
173