C8051F70X_0910 Datasheet, PDF (186/290 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F70x/71x
SFR Definition 26.23. P3MDIN: Port 3 Input Mode
Bit
7
6
5
4
3
2
1
0
Name
P3MDIN[7:0]
Type
R/W
Reset
1
1
1
1
1
1
1
1
SFR Address = 0xF4; SFR Page = F
Bit
Name
Function
7:0 P3MDIN[7:0] Analog Configuration Bits for P3.7–P3.0 (respectively).
Port pins configured for analog mode have their weak pullup, digital driver, and
digital receiver disabled.
0: Corresponding P3.n pin is configured for analog mode.
1: Corresponding P3.n pin is not configured for analog mode.
SFR Definition 26.24. P3MDOUT: Port 3 Output Mode
Bit
7
6
5
4
3
2
1
0
Name
P3MDOUT[7:0]
Type
R/W
Reset
0
0
0
0
0
0
0
0
SFR Address = 0xAF; SFR Page = F
Bit
Name
Function
7:0 P3MDOUT[7:0] Output Configuration Bits for P3.7–P3.0 (respectively).
These bits are ignored if the corresponding bit in register P3MDIN is logic 0.
0: Corresponding P3.n Output is open-drain.
1: Corresponding P3.n Output is push-pull.
186
Rev. 0.3