C8051F70X_0910 Datasheet, PDF (116/290 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F70x/71x
Table 18.1. Special Function Register (SFR) Memory Map
Addr
F8
F0
E8
E0
D8
D0
C8
C0
B8
B0
A8
A0
98
90
88
80
SFR
Page
0
F
0
F
0
F
0
F
0
F
0
F
0
F
0
F
0
F
0
F
0
F
0
F
0
F
0
F
0
F
0
F
0(8)
1(9)
2(A)
3(B)
4(C)
5(D)
6(E)
7(F)
SPI0CN
B
ADC0CN
ACC
PCA0L
P0DRV
PCA0H PCA0CPL0 PCA0CPH0
P1DRV P2DRV P3DRV
P0MAT P0MASK
P0MDIN P1MDIN P2MDIN P3MDIN
PCA0CPL1 PCA0CPH1 PCA0CPL2 PCA0CPH2
DERIVID
P1MAT
XBR0
P1MASK
XBR1
WDTCN
IT01CF
P4DRV
P4MDIN
PCA0MD
P5DRV
P5MDIN
EMI0TC
EIE1
VDM0CN
RSTSRC
EIE2
PCA0CN _{CRC0DATA PCA0CPM0 PCA0CPM1 PCA0CPM2}
PSW
TMR2CN
SMB0CN
IP
EEDATA
SMB0CF
P6DRV
REG0CN
REF0CN
P0SKIP
TMR2RLL TMR2RLH TMR2L
P1SKIP
TMR2H
SMB0DAT ADC0GTL ADC0GTH
HWID
ADC0MX
SMB0ADR SMB0ADM ADC0CF
ADC0LTL
EECNTL
ADC0L
CLKSEL
P2SKIP
EIP1
ADC0LTH
EEKEY
ADC0H
EIP2
EMI0CF
OSCICL
P3
IE
P2
SCON0
P1
P6
P5
OSCXCN ^{EEADDR FLKEY}
CS0DL CS0DH
OSCICN EMI0CN
P4
REVID
P3MDOUT
SPI0CFG
SPI0DAT
PCA0PWM SPI0CKR
P0MDOUT P1MDOUT P2MDOUT ^SFRPAGE
CS0CN CPT0CN CS0MX CPT0MD
SBUF0 _{P4MDOUT P5MDOUT P6MDOUT}
CS0CF
CPT0MX
TMR3CN TMR3RLL TMR3RLH TMR3L TMR3H CS0THL CS0THH
CRC0CN CS0SS CS0SE CRC0IN CRC0FLIP CRC0AUTO CRC0CNT
TCON
TMOD
TL0
TL1
TH0
TH1
CKCON PSCTL
P0
SP
DPL
DPH
PCON
0(8)
1(9)
2(A)
3(B)
4(C)
5(D)
6(E)
7(F)
Notes:
1. SFR addresses ending in 0x0 or 0x8 (leftmost column) are bit-addressable.
2. SFRs indicated with bold lettering and shaded cells are available on both SFR Page 0 and F.
116
Rev. 0.3