C8051F70X_0910 Datasheet, PDF (171/290 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F70x/71x
P0
P1
P2
SF Signals
PIN I/O
TX0
RX0
SCK
MISO
MOSI
NSS¹
SDA
SCL
CP0
CP0A
SYSCLK
CEX0
CEX1
CEX2
ECI
T0
T1
012345670123456701234567
001000100000000000000000
P0SKIP[0:7]
P1SKIP[0:7]
P2SKIP[0:7]
SF Signals
Port pin potentially available to peripheral
Notes:
Special Function Signals are not assigned by the crossbar. 1. NSS is only pinned out in 4-wire SPI Mode
When these signals are enabled, the CrossBar must be
manually configured to skip their corresponding port pins.
Figure 26.5. Crossbar Priority Decoder Example
Registers XBR0 and XBR1 are used to assign the digital I/O resources to the physical I/O Port pins. When
the SMBus is selected, the Crossbar assigns both pins associated with the SMBus (SDA and SCL); when
the UART is selected, the Crossbar assigns both pins associated with the UART (TX and RX). UART0 pin
assignments are fixed for bootloading purposes: UART TX0 is always assigned to P0.4; UART RX0 is
always assigned to P0.5. Standard Port I/Os appear contiguously after the prioritized functions have been
assigned.
Important Note: The SPI can be operated in either 3-wire or 4-wire modes, pending the state of the
NSSMD1–NSSMD0 bits in register SPI0CN. According to the SPI mode, the NSS signal may or may not
be routed to a Port pin.
Rev. 0.3
171