C8051F70X_0910 Datasheet, PDF (190/290 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F70x/71x
SFR Definition 26.31. P5MDIN: Port 5 Input Mode
Bit
7
6
5
4
3
2
1
0
Name
P5MDIN[7:0]
Type
R/W
Reset
1
1
1
1
1
1
1
1
SFR Address = 0xF6; SFR Page = F
Bit
Name
Function
7:0 P5MDIN[7:0] Analog Configuration Bits for P5.7–P5.0 (respectively).
Port pins configured for analog mode have their weak pullup, digital driver, and
digital receiver disabled.
0: Corresponding P5.n pin is configured for analog mode.
1: Corresponding P5.n pin is not configured for analog mode.
SFR Definition 26.32. P5MDOUT: Port 5 Output Mode
Bit
7
6
5
4
3
2
1
0
Name
P5MDOUT[7:0]
Type
R/W
Reset
0
0
0
0
0
0
0
0
SFR Address = 0x9B; SFR Page = F
Bit
Name
Function
7:0 P5MDOUT[7:0] Output Configuration Bits for P5.7–P5.0 (respectively).
These bits are ignored if the corresponding bit in register P5MDIN is logic 0.
0: Corresponding P5.n Output is open-drain.
1: Corresponding P5.n Output is push-pull.
190
Rev. 0.3