C8051F70X_0910 Datasheet, PDF (187/290 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F70x/71x
SFR Definition 26.25. P3DRV: Port 3 Drive Strength
Bit
7
6
5
4
3
2
1
0
Name
P3DRV[7:0]
Type
R/W
Reset
0
0
0
0
0
0
0
0
SFR Address = 0xFC; SFR Page = F
Bit
Name
Function
7:0 P3DRV[7:0] Drive Strength Configuration Bits for P3.7-P3.0 (respectively).
Configures digital I/O Port cells to high or low output drive strength.
0: Corresponding P3.n Output has low output drive strength.
1: Corresponding P3.n Output has high output drive strength.
SFR Definition 26.26. P4: Port 4
Bit
7
6
5
Name
Type
Reset
1
1
1
SFR Address = 0xAC; SFR Page = All Pages
Bit Name
Description
7:0 P4[7:0] Port 4 Data.
Sets the Port latch logic
value or reads the Port pin
logic state in Port cells con-
figured for digital I/O.
4
3
2
1
0
P4[7:0]
R/W
1
1
1
1
1
Write
0: Set output latch to logic
LOW.
1: Set output latch to logic
HIGH.
Read
0: P4.n Port pin is logic
LOW.
1: P4.n Port pin is logic
HIGH.
Rev. 0.3
187