C8051F70X_0910 Datasheet, PDF (165/290 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F70x/71x
26. Port Input/Output
Digital and analog resources are available through 64 I/O pins. Each of the Port pins P0.0-P2.7 can be
defined as general-purpose I/O (GPIO), assigned to one of the internal digital resources, or assigned to an
analog function as shown in Figure 26.4. The designer has complete control over which functions are
assigned, limited only by the number of physical I/O pins. This resource assignment flexibility is achieved
through the use of a Priority Crossbar Decoder. The state of a Port I/O pin can always be read in the corre-
sponding Port latch, regardless of the Crossbar settings.
The Crossbar assigns the selected internal digital resources to the I/O pins based on the Priority Decoder
(Figure 26.4 and Figure 26.5). The registers XBR0 and XBR1, defined in SFR Definition 26.1 and SFR
Definition 26.2, are used to select internal digital functions.
All Port I/Os are tolerant of voltages up to 2 V above the V_DD supply (refer to Figure 26.2 for the Port cell
circuit). The Port I/O cells are configured as either push-pull or open-drain in the Port Output Mode regis-
ters (PnMDOUT, where n = 0,1). Complete Electrical Specifications for Port I/O are given in Section
“7. Electrical Characteristics” on page 39.
H ig h e s t
P rio rity
Lowest
P rio rity
XBR0, XBR1,
PnSKIP Registers
Port Match
P0MASK, P0MAT
P1MASK, P1MAT
UART
2
SPI
4
2
SMBus
CP0
2
O u tp u ts
SYSCLK
PCA
4
T0, T1
2
8
P0 _(P0.0-P0.7)
8
P1 _(P1.0-P1.7)
Priority
Decoder
8
Digital
Crossbar
8
8
External Interrupts
EX0 and EX1
PnMDOUT,
PnMDIN , PnDRV
R e giste rs
P0
I/O
C e lls
P1
I/O
C e lls
P2
I/O
C e lls
P3
I/O
C e lls
P4
I/O
C e lls
P5
I/O
C e lls
P6 I/O Cells
(digital only)
To CS0
To Analog Peripherals
(ADC0, CP0, VREF, XTAL)
Figure 26.1. Port I/O Functional Block Diagram
P0.0
P0.7
P1.0
P1.7
P2.0
P2.7
P3.0
P3.7
P4.0
P4.7
P5.0
P5.7
P6.0
P6.5
Rev. 0.3
165