C8051F70X_0910 Datasheet, PDF (220/290 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F70x/71x
Table 28.5. SMBus Status Decoding With Hardware ACK Generation Disabled
(EHACK = 0) (Continued)
Values Read
Values to
Write
Current SMbus State
Typical Response Options
0010
0
1
X
Lost arbitration while attempt-
ing a repeated START.
Abort failed transfer.
Reschedule failed transfer.
0001
0
1
X
Lost arbitration due to a
detected STOP.
Abort failed transfer.
Reschedule failed transfer.
0000
1
1
X
Lost arbitration while transmit-
ting a data byte as master.
Abort failed transfer.
Reschedule failed transfer.
00X —
1 0 X 1110
00X —
1 0 X 1110
000 —
1 0 0 1110
Table 28.6. SMBus Status Decoding With Hardware ACK Generation Enabled
(EHACK = 1)
Values Read
Values to
Write
Current SMbus State
Typical Response Options
1110
0
0
X
A master START was gener-
ated.
Load slave address + R/W into
SMB0DAT.
0 0 X 1100
A master data or address byte Set STA to restart transfer.
0 0 0 was transmitted; NACK
received.
Abort transfer.
1 0 X 1110
01X —
Load next data byte into
SMB0DAT.
0 0 X 1100
End transfer with STOP.
01X —
1100
0
0
1
A master data or address byte
was transmitted; ACK
End transfer with STOP and start
another transfer.
1
1
X
—
received.
Send repeated START.
1 0 X 1110
Switch to Master Receiver Mode 0 0 1 1000
(clear SI without writing new data
to SMB0DAT). Set ACK for initial
data byte.
220
Rev. 0.3