C8051F70X_0910 Datasheet, PDF (26/290 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F70x/71x
3. Pin Definitions
Table 3.1. Pin Definitions for the C8051F70x/71x
Name
V_DD
GND
RST /
64-Pin 48-Pin
Packages Packages
8, 24, 41, 8, 20, 44
57
9, 25, 40, 9, 21, 30,
56
43
58
45
Type
D I/O
Description
Power Supply Voltage.
Ground.
Device Reset. Open-drain output of internal POR or V_DD
monitor.
C2CK
C2D
59
D I/O Clock signal for the C2 Debug Interface.
46
D I/O or Bi-directional data signal for the C2 Debug Interface.
A In
P0.0 /
55
D I/O
42
D I/O or Port 0.0.
A In
VREF
P0.1/
54
A In External VREF input.
41
D I/O or Port 0.1.
A In
AGND
P0.2 /
53
External AGND input.
40
D I/O or Port 0.2.
A In
XTAL1
P0.3 /
52
A In External Clock Pin. This pin can be used for crystal clock
mode.
39
D I/O or Port 0.3.
A In
XTAL2
P0.4
51
P0.5
50
P0.6
49
A I/O or External Clock Pin. This pin can be used for RC, crystal,
D In and CMOS clock modes.
38
D I/O or Port 0.4.
A In
37
D I/O or Port 0.5.
A In
36
D I/O or Port 0.6.
AI
26
Rev. 0.3