C8051F70X_0910 Datasheet, PDF (111/290 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F70x/71x
Table 16.1. AC Parameters for External Memory Interface
Parameter
Description
Min*
T_ACS
T_ACW
T_ACH
T_ALEH
T_ALEL
T_WDS
T_WDH
T_RDS
T_RDH
Address/Control Setup Time
Address/Control Pulse Width
Address/Control Hold Time
Address Latch Enable High Time
Address Latch Enable Low Time
Write Data Setup Time
Write Data Hold Time
Read Data Setup Time
Read Data Hold Time
0
T_SYSCLK
0
T_SYSCLK
T_SYSCLK
T_SYSCLK
0
20
0
Note: T_SYSCLK is equal to one period of the device system clock (SYSCLK).
Max*
3 x T_SYSCLK
16 x T_SYSCLK
3 x T_SYSCLK
4 x T_SYSCLK
4 x T_SYSCLK
19 x T_SYSCLK
3 x T_SYSCLK
—
—
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
Rev. 0.3
111