C8051F70X_0910 Datasheet, PDF (10/290 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F70x/71x
Figure 28.8. Typical Slave Read Sequence .......................................................... 217
29. Enhanced Serial Peripheral Interface (SPI0)
Figure 29.1. SPI Block Diagram ............................................................................ 223
Figure 29.2. Multiple-Master Mode Connection Diagram ...................................... 225
Figure 29.3. 3-Wire Single Master and 3-Wire Single Slave Mode
Connection Diagram .......................................................................... 226
Figure 29.4. 4-Wire Single Master Mode and 4-Wire Slave Mode
Connection Diagram .......................................................................... 226
Figure 29.5. Master Mode Data/Clock Timing ....................................................... 228
Figure 29.6. Slave Mode Data/Clock Timing (CKPHA = 0) ................................... 228
Figure 29.7. Slave Mode Data/Clock Timing (CKPHA = 1) ................................... 229
Figure 29.8. SPI Master Timing (CKPHA = 0) ....................................................... 233
Figure 29.9. SPI Master Timing (CKPHA = 1) ....................................................... 233
Figure 29.10. SPI Slave Timing (CKPHA = 0) ....................................................... 234
Figure 29.11. SPI Slave Timing (CKPHA = 1) ....................................................... 234
30. UART0
Figure 30.1. UART0 Block Diagram ...................................................................... 236
Figure 30.2. UART0 Baud Rate Logic ................................................................... 237
Figure 30.3. UART Interconnect Diagram ............................................................. 238
Figure 30.4. 8-Bit UART Timing Diagram .............................................................. 238
Figure 30.5. 9-Bit UART Timing Diagram .............................................................. 239
Figure 30.6. UART Multi-Processor Mode Interconnect Diagram ......................... 240
31. Timers
Figure 31.1. T0 Mode 0 Block Diagram ................................................................. 247
Figure 31.2. T0 Mode 2 Block Diagram ................................................................. 248
Figure 31.3. T0 Mode 3 Block Diagram ................................................................. 249
Figure 31.4. Timer 2 16-Bit Mode Block Diagram ................................................. 254
Figure 31.5. Timer 2 8-Bit Mode Block Diagram ................................................... 255
Figure 31.7. Timer 3 16-Bit Mode Block Diagram ................................................. 260
Figure 31.8. Timer 3 8-Bit Mode Block Diagram ................................................... 261
Figure 31.9. Timer 3 Capture Mode Block Diagram .............................................. 262
32. Programmable Counter Array
Figure 32.1. PCA Block Diagram ........................................................................... 266
Figure 32.2. PCA Counter/Timer Block Diagram ................................................... 267
Figure 32.3. PCA Interrupt Block Diagram ............................................................ 268
Figure 32.4. PCA Capture Mode Diagram ............................................................. 270
Figure 32.5. PCA Software Timer Mode Diagram ................................................. 271
Figure 32.6. PCA High-Speed Output Mode Diagram ........................................... 272
Figure 32.7. PCA Frequency Output Mode ........................................................... 273
Figure 32.8. PCA 8-Bit PWM Mode Diagram ........................................................ 275
Figure 32.9. PCA 9, 10 and 11-Bit PWM Mode Diagram ...................................... 276
Figure 32.10. PCA 16-Bit PWM Mode ................................................................... 277
33. C2 Interface
Figure 33.1. Typical C2CK Pin Sharing ................................................................. 287
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Rev. 0.3