C8051F70X_0910 Datasheet, PDF (170/290 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F70x/71x
26.3. Priority Crossbar Decoder
The Priority Crossbar Decoder (Figure 26.4) assigns a priority to each I/O function, starting at the top with
UART0. When a digital resource is selected, the least-significant unassigned Port pin is assigned to that
resource (excluding UART0, which is always at pins 4 and 5). If a Port pin is assigned, the Crossbar skips
that pin when assigning the next selected resource. Additionally, the Crossbar will skip Port pins whose
associated bits in the PnSKIP registers are set. The PnSKIP registers allow software to skip Port pins that
are to be used for analog input, dedicated functions, or GPIO.
Important Note on Crossbar Configuration: If a Port pin is claimed by a peripheral without use of the
Crossbar, its corresponding PnSKIP bit should be set. This applies to P0.0 if VREF is used, P0.1 if AGND
is used, P0.3 and/or P0.2 if the external oscillator circuit is enabled, P0.6 if the ADC is configured to use
the external conversion start signal (CNVSTR), and any selected ADC or Comparator inputs. The Cross-
bar skips selected pins as if they were already assigned, and moves to the next unassigned pin.
Figure 26.5 shows the Crossbar Decoder priority with pins P0.2 and P0.6 skipped (P0SKIP = 0x44).
P0
P1
P2
SF Signals
PIN I/O
TX0
RX0
SCK
M IS O
MOSI
NS S ¹
SDA
SCL
CP0
CP0A
S YS CL K
CEX 0
CEX 1
CEX 2
ECI
T0
T1
012345670123456701234567
SF Signals
P ort pin potentially available to peripheral
S pecial Function S ignals are not ass igned by the
c ros s bar. W hen thes e s ignals are enabled, the
Cros s bar m us t be m anually c onfigured to s k ip
their c orres ponding port pins .
Notes:
1. NS S is only pinned out in 4-wire S P I M ode
Figure 26.4. Crossbar Priority Decoder—Possible Pin Assignments
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Rev. 0.3