C8051F70X_0910 Datasheet, PDF (28/290 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F70x/71x
Table 3.1. Pin Definitions for the C8051F70x/71x (Continued)
Name
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
P4.0
P4.1
P4.2
P4.3
P4.4
P4.5
P4.6
P4.7
P5.0
64-Pin 48-Pin Type
Packages Packages
Description
29
D I/O or Port 3.0.
A In Cap Sense input pin 9.
28
D I/O or Port 3.1.
A In Cap Sense input pin 10.
27
D I/O or Port 3.2.
A In Cap Sense input pin 11.
26
D I/O or Port 3.3.
A In Cap Sense input pin 12.
23
19
D I/O or Port 3.4.
A In Cap Sense input pin 13.
22
18
D I/O or Port 3.5.
A In Cap Sense input pin 14.
21
17
D I/O or Port 3.6.
A In Cap Sense input pin 15.
20
16
D I/O or Port 3.7.
A In Cap Sense input pin 16.
19
15
D I/O or Port 4.0.
A In Cap Sense input pin 17.
18
14
D I/O or Port 4.1.
A In Cap Sense input pin 18.
17
13
D I/O or Port 4.2.
A In Cap Sense input pin 19.
16
12
D I/O or Port 4.3.
A In Cap Sense input pin 20.
15
D I/O or Port 4.4.
A In Cap Sense input pin 21.
14
D I/O or Port 4.5.
A In Cap Sense input pin 22.
13
D I/O or Port 4.6.
A In Cap Sense input pin 23.
12
D I/O or Port 4.7.
A In Cap Sense input pin 24.
11
11
D I/O or Port 5.0.
A In Cap Sense input pin 25.
28
Rev. 0.3