C8051F70X_0910 Datasheet, PDF (188/290 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F70x/71x
SFR Definition 26.27. P4MDIN: Port 4 Input Mode
Bit
7
6
5
4
3
2
1
0
Name
P4MDIN[7:0]
Type
R/W
Reset
1
1
1
1
1
1
1
1
SFR Address = 0xF5; SFR Page = F
Bit
Name
Function
7:0 P4MDIN[7:0] Analog Configuration Bits for P4.7–P4.0 (respectively).
Port pins configured for analog mode have their weak pullup, digital driver, and
digital receiver disabled.
0: Corresponding P4.n pin is configured for analog mode.
1: Corresponding P4.n pin is not configured for analog mode.
SFR Definition 26.28. P4MDOUT: Port 4 Output Mode
Bit
7
6
5
4
3
2
1
0
Name
P4MDOUT[7:0]
Type
R/W
Reset
0
0
0
0
0
0
0
0
SFR Address = 0x9A; SFR Page = F
Bit
Name
Function
7:0 P4MDOUT[7:0] Output Configuration Bits for P4.7–P4.0 (respectively).
These bits are ignored if the corresponding bit in register P4MDIN is logic 0.
0: Corresponding P4.n Output is open-drain.
1: Corresponding P4.n Output is push-pull.
188
Rev. 0.3