C8051F70X_0910 Datasheet, PDF (235/290 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F70x/71x
Table 29.1. SPI Slave Timing Parameters
Parameter Description
Min
Max
Units
Master Mode Timing (See Figure 29.8 and Figure 29.9)
T_MCKH
T_MCKL
T_MIS
T_MIH
SCK High Time
SCK Low Time
MISO Valid to SCK Shift Edge
SCK Shift Edge to MISO Change
1 x T_SYSCLK
—
ns
1 x T_SYSCLK
—
ns
1 x T_SYSCLK + 20
—
ns
0
—
ns
Slave Mode Timing (See Figure 29.10 and Figure 29.11)
T_SE
T_SD
T_SEZ
T_SDZ
T_CKH
T_CKL
T_SIS
T_SIH
T_SOH
T_SLH
NSS Falling to First SCK Edge
Last SCK Edge to NSS Rising
NSS Falling to MISO Valid
NSS Rising to MISO High-Z
SCK High Time
SCK Low Time
MOSI Valid to SCK Sample Edge
SCK Sample Edge to MOSI Change
SCK Shift Edge to MISO Change
Last SCK Edge to MISO Change
(CKPHA = 1 ONLY)
2 x T_SYSCLK
2 x T_SYSCLK
—
—
5 x T_SYSCLK
5 x T_SYSCLK
2 x T_SYSCLK
2 x T_SYSCLK
—
6 x T_SYSCLK
—
ns
—
ns
4 x T_SYSCLK ns
4 x T_SYSCLK ns
—
ns
—
ns
—
ns
—
ns
4 x T_SYSCLK ns
8 x T_SYSCLK ns
Note: T_SYSCLK is equal to one period of the device system clock (SYSCLK).
Rev. 0.3
235