C8051F70X_0910 Datasheet, PDF (191/290 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F70x/71x
SFR Definition 26.33. P5DRV: Port 5 Drive Strength
Bit
7
6
5
4
3
2
1
0
Name
P5DRV[7:0]
Type
R/W
Reset
0
0
0
0
0
0
0
0
SFR Address = 0xFE; SFR Page = F
Bit
Name
Function
7:0 P5DRV[7:0] Drive Strength Configuration Bits for P5.7-P5.0 (respectively).
Configures digital I/O Port cells to high or low output drive strength.
0: Corresponding P5.n Output has low output drive strength.
1: Corresponding P5.n Output has high output drive strength.
SFR Definition 26.34. P6: Port 6
Bit
7
6
5
4
3
2
1
0
Name
P6[5:0]
Type
R
R
R/W
Reset
0
0
1
1
1
1
1
1
SFR Address = 0xB2; SFR Page = All Pages
Bit Name
Description
Write
7:6 Unused Read = 00b; Write = Don’t Care
5:0 P6[5:0] Port 6 Data.
0: Set output latch to logic
Sets the Port latch logic
LOW.
value or reads the Port pin ^{1: Set output latch to logic}
logic state in Port cells con- ^HIGH.
figured for digital I/O.
Read
0: P6.n Port pin is logic
LOW.
1: P6.n Port pin is logic
HIGH.
Rev. 0.3
191