C8051F70X_0910 Datasheet, PDF (12/290 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F70x/71x
18. Special Function Registers
Table 18.1. Special Function Register (SFR) Memory Map .................................. 116
Table 18.2. Special Function Registers ................................................................. 117
19. Interrupts
Table 19.1. Interrupt Summary .............................................................................. 124
20. Flash Memory
Table 20.1. Flash Security Summary .................................................................... 135
21. EEPROM
22. Power Management Modes
23. Reset Sources
24. Watchdog Timer
25. Oscillators and Clock Selection
26. Port Input/Output
Table 26.1. Port I/O Assignment for Analog Functions ......................................... 168
Table 26.2. Port I/O Assignment for Digital Functions ........................................... 169
Table 26.3. Port I/O Assignment for External Event Trigger Functions ................. 169
27. Cyclic Redundancy Check Unit (CRC0)
Table 27.1. Example 16-bit CRC Outputs ............................................................. 194
Table 27.2. Example 32-bit CRC Outputs ............................................................. 195
28. SMBus
Table 28.1. SMBus Clock Source Selection .......................................................... 205
Table 28.2. Minimum SDA Setup and Hold Times ................................................ 206
Table 28.3. Sources for Hardware Changes to SMB0CN ..................................... 210
Table 28.4. Hardware Address Recognition Examples (EHACK = 1) ................... 211
Table 28.5. SMBus Status Decoding With Hardware ACK Generation Disabled
(EHACK = 0) ....................................................................................... 218
Table 28.6. SMBus Status Decoding With Hardware ACK Generation Enabled
(EHACK = 1) ....................................................................................... 220
29. Enhanced Serial Peripheral Interface (SPI0)
Table 29.1. SPI Slave Timing Parameters ............................................................ 235
30. UART0
Table 30.1. Timer Settings for Standard Baud Rates
Using The Internal 24.5 MHz Oscillator .............................................. 243
Table 30.2. Timer Settings for Standard Baud Rates
Using an External 22.1184 MHz Oscillator ......................................... 243
31. Timers
32. Programmable Counter Array
Table 32.1. PCA Timebase Input Options ............................................................. 267
Table 32.2. PCA0CPM and PCA0PWM Bit Settings for PCA
Capture/Compare Modules ................................................................ 269
33. C2 Interface
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