C8051F70X_0910 Datasheet, PDF (124/290 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F70x/71x
Interrupt Source
Table 19.1. Interrupt Summary
Interrupt Priority Pending Flag
Vector Order
Enable
Flag
Priority
Control
Reset
External Interrupt 0
(INT0)
Timer 0 Overflow
External Interrupt 1
(INT1)
Timer 1 Overflow
UART0
Timer 2 Overflow
SPI0
0x0000 Top
0x0003 0
0x000B 1
0x0013 2
0x001B 3
0x0023 4
0x002B 5
0x0033 6
SMB0
0x003B 7
Port Match
0x0043 8
ADC0
0x0043 9
Window Compare
ADC0
0x004B 10
Conversion Complete
Programmable
0x0053 11
Counter Array
Comparator0
0x005B 12
RESERVED
Timer 3 Overflow
0x0073 14
CS0 Conversion Com- 0x007B 15
plete
CS0 Greater Than
0x0083 16
None
IE0 (TCON.1)
N/A N/A Always Always
Enabled Highest
Y Y EX0 (IE.0) PX0 (IP.0)
TF0 (TCON.5)
IE1 (TCON.3)
Y Y ET0 (IE.1) PT0 (IP.1)
Y Y EX1 (IE.2) PX1 (IP.2)
TF1 (TCON.7)
Y Y ET1 (IE.3) PT1 (IP.3)
RI0 (SCON0.0)
Y N ES0 (IE.4) PS0 (IP.4)
TI0 (SCON0.1)
TF2H (TMR2CN.7)
Y N ET2 (IE.5) PT2 (IP.5)
TF2L (TMR2CN.6)
SPIF (SPI0CN.7)
Y
ESPI0 PSPI0
WCOL (SPI0CN.6)
MODF (SPI0CN.5)
(IE.6)
(IP.6)
RXOVRN (SPI0CN.4)
SI (SMB0CN.0)
Y N ESMB0 PSMB0
(EIE1.0) (EIP1.0)
None
N/A N/A EMAT
PMAT
(EIE1.1) (EIP1.1)
AD0WINT (ADC0CN.3) Y N EWADC0 PWADC0
(EIE1.2) (EIP1.2)
AD0INT (ADC0CN.5) Y N EADC0 PADC0
(EIE1.3) (EIP1.3)
CF (PCA0CN.7)
Y N EPCA0 PPCA0
CCFn (PCA0CN.n)
(EIE1.4) (EIP1.4)
CP0FIF (CPT0CN.4)
CP0RIF (CPT0CN.5)
N N ECP0
PCP0
(EIE1.5) (EIP1.5)
TF3H (TMR3CN.7)
N N ET3
PT3
TF3L (TMR3CN.6)
(EIE1.7) (EIP1.7)
CS0INT (CS0CN.5)
N N ECSCPT PSCCPT
(EIE2.0) (EIP2.0)
CS0CMPF (CS0CN.0) N N ECSGRT PSCGRT
(EIE2.1) (EIP2.1)
19.2. Interrupt Register Descriptions
The SFRs used to enable the interrupt sources and set their priority level are described in this section.
Refer to the data sheet section associated with a particular on-chip peripheral for information regarding
valid interrupt conditions for the peripheral and the behavior of its interrupt-pending flag(s).
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