C8051F70X_0910 Datasheet, PDF (130/290 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F70x/71x
SFR Definition 19.6. EIP2: Extended Interrupt Priority 2
Bit
Name
Type
Reset
7
Reserved
R
0
6
Reserved
R
0
5
Reserved
R
0
4
Reserved
R
0
3
Reserved
R
0
2
Reserved
R
0
1
PSCGRT
R/W
0
0
PSCCPT
R/W
0
SFR Address = 0xCF; SFR Page = F
Bit Name
Function
7:2 Reserved Reserved. Must write to 0.
1 PSCGRT _{Capacitive Sense Greater Than Comparator Priority Control.}
This bit sets the priority of the Capacitive Sense Greater Than Comparator interrupt.
0: CS0 Greater Than Comparator interrupt set to low priority level.
1: CS0 Greater Than Comparator set to high priority level.
0 PSCCPT _{Capacitive Sense Conversion Complete Priority Control.}
This bit sets the priority of the Capacitive Sense Conversion Complete interrupt.
0: CS0 Conversion Complete set to low priority level.
1: CS0 Conversion Complete set to high priority level.
130
Rev. 0.3